sparc64: Add missing hardware capabilities for M7

Some M7 hardware capabilities were not being reported
correctly. This commit fixes the issue by adding definitions
for all the missing capabilities from both the Machine
Descriptor and the Compatibility Feature Register.

Orabug: 25555746

Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Reviewed-by: Shannon Nelson <shannon.nelson@oracle.com>
Reviewed-by: Khalid Aziz <khalid.aziz@oracle.com>
Signed-off-by: Allen Pais <allen.pais@oracle.com>

diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h
index 5b751f253d15c74e1519bc2eb293f619a9620428..b295b47ea2443aadb9e9bb87ed00fc04be0ce605 100644 (file)
--- a/arch/sparc/include/asm/elf_64.h
+++ b/arch/sparc/include/asm/elf_64.h
@@ -96,6 +96,13 @@
  */
 #define HWCAP_SPARC_CRYPTO     0x04000000 /* CRYPTO insns available */
 #define HWCAP_SPARC_ADI                0x08000000 /* ADI available */
+#define HWCAP_SPARC_VIS3B      0x10000000 /* VIS3B insns available */
+#define HWCAP_SPARC_PAUSE_NSEC 0x20000000 /* Time based pause available */
+#define HWCAP_SPARC_MWAIT      0x40000000 /* MWAIT insn available */
+#define HWCAP_SPARC_SPARC5     0x80000000 /* SPARC5 insns available */
+
+/* Virtual Address Masking available */
+#define HWCAP_SPARC_VAMASK     0x0000000100000000UL
 
 #define CORE_DUMP_USE_REGSET
 

diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 0ecfaa69c6ea10e3f3970bbbc9252e2ca18aab66..0c32514967218b4e6048c7e232e0048d4ef3979c 100644 (file)
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -390,16 +390,20 @@ static const char *hwcaps[] = {
 
        /* These strings are as they appear in the machine description
         * 'hwcap-list' property for cpu nodes.
+        * Note: Virtual address masking (vamask) appears in the machine
+        *       description cpu node as va-mask-nz-mask and va-mask-z-mask
+        *       properties.
         */
        "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
        "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
        "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
-       "adp",
+       "adp", "vis3b", "pause-nsec", "mwait", "sparc5", "vamask"
 };
 
 static const char *crypto_hwcaps[] = {
        "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
-       "sha512", "mpmul", "montmul", "montsqr", "crc32c",
+       "sha512", "mpmul", "montmul", "montsqr", "crc32c", "xmpmul",
+       "xmontmul", "xmontsqr"
 };
 
 void cpucap_info(struct seq_file *m)
@@ -549,6 +553,10 @@ static void __init init_sparc64_elf_hwcap(void)
                    sun4v_chip_type == SUN4V_CHIP_SPARC_S7 ||
                    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
                        cap |= HWCAP_SPARC_N2;
+               if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
+                   sun4v_chip_type == SUN4V_CHIP_SPARC_S7)
+                       cap |= (HWCAP_SPARC_VAMASK |
+                               AV_SPARC_FSMULD);
        }
 
        cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
@@ -592,8 +600,19 @@ static void __init init_sparc64_elf_hwcap(void)
                        if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
                            sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
                            sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
+                           sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
                            sun4v_chip_type == SUN4V_CHIP_SPARC_S7)
                                cap |= AV_SPARC_VIS3;
+                       if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
+                           sun4v_chip_type == SUN4V_CHIP_SPARC_S7)
+                               cap |= (AV_SPARC_IMA | AV_SPARC_PAUSE |
+                                       AV_SPARC_CBCOND |
+                                       HWCAP_SPARC_CRYPTO |
+                                       HWCAP_SPARC_ADI |
+                                       HWCAP_SPARC_VIS3B |
+                                       HWCAP_SPARC_PAUSE_NSEC |
+                                       HWCAP_SPARC_MWAIT |
+                                       HWCAP_SPARC_SPARC5);
                }
        }
        sparc64_elf_hwcap = cap | mdesc_caps;