rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
                rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
                rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0);
-               if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
-                       rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
+               rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
 
                rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
        }
                rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
                rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
                rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1);
-               if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
-                       rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
+               rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
 
                rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);