drm/vc4: plane: Change ptr0_offset to an array

The BCM2712 will have a fairly different dlist, that will feature one
Pointer 0 word for each plane.

Let's prepare by changing the ptr0_offset variable that holds the offset
in a dlist of the pointer 0 word to an array.

Signed-off-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240621152055.4180873-27-dave.stevenson@raspberrypi.com
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>

diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 294858d59e2742e29cd7db162ed7c0508f9e0a81..559118824bf795cafd79d319699d071c6a086446 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -15,6 +15,7 @@
 #include <drm/drm_debugfs.h>
 #include <drm/drm_device.h>
 #include <drm/drm_encoder.h>
+#include <drm/drm_fourcc.h>
 #include <drm/drm_gem_dma_helper.h>
 #include <drm/drm_managed.h>
 #include <drm/drm_mm.h>
@@ -400,7 +401,7 @@ struct vc4_plane_state {
         */
        u32 pos0_offset;
        u32 pos2_offset;
-       u32 ptr0_offset;
+       u32 ptr0_offset[DRM_FORMAT_MAX_PLANES];
        u32 lbm_offset;
 
        /* Offset where the plane's dlist was last stored in the

diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index a61a29f02be0833fde1e50301910b5203db2a376..a4965226595de1e76b6cc395362d01b3afaf49c4 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -1256,7 +1256,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
         *
         * The pointers may be any byte address.
         */
-       vc4_state->ptr0_offset = vc4_state->dlist_count;
+       vc4_state->ptr0_offset[0] = vc4_state->dlist_count;
        for (i = 0; i < num_planes; i++)
                vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
 
@@ -1460,13 +1460,13 @@ void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
         * scanout will start from this address as soon as the FIFO
         * needs to refill with pixels.
         */
-       writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
+       writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
 
        /* Also update the CPU-side dlist copy, so that any later
         * atomic updates that don't do a new modeset on our plane
         * also use our updated address.
         */
-       vc4_state->dlist[vc4_state->ptr0_offset] = addr;
+       vc4_state->dlist[vc4_state->ptr0_offset[0]] = addr;
 
        drm_dev_exit(idx);
 }
@@ -1530,8 +1530,8 @@ static void vc4_plane_atomic_async_update(struct drm_plane *plane,
                new_vc4_state->dlist[vc4_state->pos0_offset];
        vc4_state->dlist[vc4_state->pos2_offset] =
                new_vc4_state->dlist[vc4_state->pos2_offset];
-       vc4_state->dlist[vc4_state->ptr0_offset] =
-               new_vc4_state->dlist[vc4_state->ptr0_offset];
+       vc4_state->dlist[vc4_state->ptr0_offset[0]] =
+               new_vc4_state->dlist[vc4_state->ptr0_offset[0]];
 
        /* Note that we can't just call vc4_plane_write_dlist()
         * because that would smash the context data that the HVS is
@@ -1541,8 +1541,8 @@ static void vc4_plane_atomic_async_update(struct drm_plane *plane,
               &vc4_state->hw_dlist[vc4_state->pos0_offset]);
        writel(vc4_state->dlist[vc4_state->pos2_offset],
               &vc4_state->hw_dlist[vc4_state->pos2_offset]);
-       writel(vc4_state->dlist[vc4_state->ptr0_offset],
-              &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
+       writel(vc4_state->dlist[vc4_state->ptr0_offset[0]],
+              &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
 
        drm_dev_exit(idx);
 }
@@ -1569,7 +1569,7 @@ static int vc4_plane_atomic_async_check(struct drm_plane *plane,
        if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
            old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
            old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
-           old_vc4_state->ptr0_offset != new_vc4_state->ptr0_offset ||
+           old_vc4_state->ptr0_offset[0] != new_vc4_state->ptr0_offset[0] ||
            vc4_lbm_size(plane->state) != vc4_lbm_size(new_plane_state))
                return -EINVAL;
 
@@ -1579,7 +1579,7 @@ static int vc4_plane_atomic_async_check(struct drm_plane *plane,
        for (i = 0; i < new_vc4_state->dlist_count; i++) {
                if (i == new_vc4_state->pos0_offset ||
                    i == new_vc4_state->pos2_offset ||
-                   i == new_vc4_state->ptr0_offset ||
+                   i == new_vc4_state->ptr0_offset[0] ||
                    (new_vc4_state->lbm_offset &&
                     i == new_vc4_state->lbm_offset))
                        continue;