if (!test_bit(ST_CAPT_APPLY_CFG, &fimc->state))
                return 0;
 
-       spin_lock(&ctx->slock);
        fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
+
        ret = fimc_set_scaler_info(ctx);
-       if (ret == 0) {
-               fimc_hw_set_prescaler(ctx);
-               fimc_hw_set_mainscaler(ctx);
-               fimc_hw_set_target_format(ctx);
-               fimc_hw_set_rotation(ctx);
-               fimc_prepare_dma_offset(ctx, &ctx->d_frame);
-               fimc_hw_set_out_dma(ctx);
-               if (fimc->variant->has_alpha)
-                       fimc_hw_set_rgb_alpha(ctx);
-               clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
-       }
-       spin_unlock(&ctx->slock);
+       if (ret)
+               return ret;
+
+       fimc_hw_set_prescaler(ctx);
+       fimc_hw_set_mainscaler(ctx);
+       fimc_hw_set_target_format(ctx);
+       fimc_hw_set_rotation(ctx);
+       fimc_prepare_dma_offset(ctx, &ctx->d_frame);
+       fimc_hw_set_out_dma(ctx);
+       if (fimc->variant->has_alpha)
+               fimc_hw_set_rgb_alpha(ctx);
+
+       clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
        return ret;
 }
 
 
        INIT_LIST_HEAD(&vid_cap->pending_buf_q);
        INIT_LIST_HEAD(&vid_cap->active_buf_q);
-       spin_lock_init(&ctx->slock);
        vid_cap->ctx = ctx;
 
        q = &fimc->vid_cap.vbq;
 
        if (!fimc_m2m_pending(fimc))
                return 0;
 
-       fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
+       fimc_ctx_state_set(FIMC_CTX_SHUT, ctx);
 
        ret = wait_event_timeout(fimc->irq_queue,
                           !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
                        spin_unlock(&fimc->slock);
                        fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 
-                       spin_lock(&ctx->slock);
                        if (ctx->state & FIMC_CTX_SHUT) {
                                ctx->state &= ~FIMC_CTX_SHUT;
                                wake_up(&fimc->irq_queue);
                        }
-                       spin_unlock(&ctx->slock);
+                       return IRQ_HANDLED;
                }
-               return IRQ_HANDLED;
        } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
                fimc_capture_irq_handler(fimc,
                                 !test_bit(ST_CAPT_JPEG, &fimc->state));
        spin_lock_irqsave(&fimc->slock, flags);
        set_bit(ST_M2M_PEND, &fimc->state);
 
-       spin_lock(&ctx->slock);
        ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
        ret = fimc_prepare_config(ctx, ctx->state);
        if (ret)
                fimc_hw_set_input_path(ctx);
                fimc_hw_set_in_dma(ctx);
                ret = fimc_set_scaler_info(ctx);
-               if (ret) {
-                       spin_unlock(&fimc->slock);
+               if (ret)
                        goto dma_unlock;
-               }
                fimc_hw_set_prescaler(ctx);
                fimc_hw_set_mainscaler(ctx);
                fimc_hw_set_target_format(ctx);
                       FIMC_SRC_FMT | FIMC_DST_FMT);
        fimc_hw_activate_input_dma(fimc, true);
 dma_unlock:
-       spin_unlock(&ctx->slock);
        spin_unlock_irqrestore(&fimc->slock, flags);
 }
 
        unsigned long flags;
        int ret;
 
-       spin_lock_irqsave(&ctx->slock, flags);
+       spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
        ret = __fimc_s_ctrl(ctx, ctrl);
-       spin_unlock_irqrestore(&ctx->slock, flags);
+       spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
 
        return ret;
 }
        ctx->scaler.enabled = 1;
 
        if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
-               fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
+               fimc_ctx_state_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
        else
-               fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
+               fimc_ctx_state_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
 
        dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
 
        f->width  = cr->c.width;
        f->height = cr->c.height;
 
-       fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
+       fimc_ctx_state_set(FIMC_PARAMS, ctx);
 
        return 0;
 }
        ctx->flags = 0;
        ctx->in_path = FIMC_DMA;
        ctx->out_path = FIMC_DMA;
-       spin_lock_init(&ctx->slock);
 
        ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
        if (IS_ERR(ctx->m2m_ctx)) {
 
 
 /**
  * fimc_ctx - the device context data
- * @slock:             spinlock protecting this data structure
  * @s_frame:           source frame properties
  * @d_frame:           destination frame properties
  * @out_order_1p:      output 1-plane YCBCR order
  * @ctrls_rdy:         true if the control handler is initialized
  */
 struct fimc_ctx {
-       spinlock_t              slock;
        struct fimc_frame       s_frame;
        struct fimc_frame       d_frame;
        u32                     out_order_1p;
        return ret;
 }
 
-static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx)
+static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&ctx->slock, flags);
+       spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
        ctx->state |= state;
-       spin_unlock_irqrestore(&ctx->slock, flags);
+       spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
 }
 
 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
        unsigned long flags;
        bool ret;
 
-       spin_lock_irqsave(&ctx->slock, flags);
+       spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
        ret = (ctx->state & mask) == mask;
-       spin_unlock_irqrestore(&ctx->slock, flags);
+       spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
        return ret;
 }