arm64: dts: renesas: r8a779f0: Add CA55 operating points

Add operating points for running the Cortex-A55 CPU cores on R-Car S4-8
at various speeds, up to the maximum supported frequency (1200 MHz).

R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters.
CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ.
CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ.

As the two sets of clusters are driven by separate clocks, this requires
specifying two separate tables (using the same operating performance
point values), with "opp-shared" to indicate that the CPU cores in each
set share state.

Based on a patch in the BSP by Tho Vu.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/ae78351d702a53702a1d5fa26675fe982b99cdf5.1669817508.git.geert+renesas@glider.be

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 67a4f2d4480d8450b6c8b872a93fc55906199537..ac294168c86785dbd22a6f5e1ce45d2f723240f9 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -14,6 +14,60 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
+       cluster01_opp: opp-table-0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+                       opp-suspend;
+               };
+       };
+
+       cluster23_opp: opp-table-1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+                       opp-suspend;
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -65,6 +119,7 @@
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+                       operating-points-v2 = <&cluster01_opp>;
                };
 
                a55_1: cpu@100 {
@@ -76,6 +131,7 @@
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+                       operating-points-v2 = <&cluster01_opp>;
                };
 
                a55_2: cpu@10000 {
@@ -87,6 +143,7 @@
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+                       operating-points-v2 = <&cluster01_opp>;
                };
 
                a55_3: cpu@10100 {
@@ -98,6 +155,7 @@
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+                       operating-points-v2 = <&cluster01_opp>;
                };
 
                a55_4: cpu@20000 {
@@ -109,6 +167,7 @@
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+                       operating-points-v2 = <&cluster23_opp>;
                };
 
                a55_5: cpu@20100 {
@@ -120,6 +179,7 @@
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+                       operating-points-v2 = <&cluster23_opp>;
                };
 
                a55_6: cpu@30000 {
@@ -131,6 +191,7 @@
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+                       operating-points-v2 = <&cluster23_opp>;
                };
 
                a55_7: cpu@30100 {
@@ -142,6 +203,7 @@
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+                       operating-points-v2 = <&cluster23_opp>;
                };
 
                L3_CA55_0: cache-controller-0 {