wfx_control_reg_read(wdev, &cur);
        prev = atomic_xchg(&wdev->hif.ctrl_reg, cur);
        complete(&wdev->hif.ctrl_ready);
-       queue_work(system_highpri_wq, &wdev->hif.bh);
+       queue_work(wdev->bh_wq, &wdev->hif.bh);
 
        if (!(cur & CTRL_NEXT_LEN_MASK))
                dev_err(wdev->dev, "unexpected control register value: length field is 0: %04x\n",
 /* Driver want to send data */
 void wfx_bh_request_tx(struct wfx_dev *wdev)
 {
-       queue_work(system_highpri_wq, &wdev->hif.bh);
+       queue_work(wdev->bh_wq, &wdev->hif.bh);
 }
 
 /* If IRQ is not available, this function allow to manually poll the control register and simulate
        u32 reg;
 
        WARN(!wdev->poll_irq, "unexpected IRQ polling can mask IRQ");
-       flush_workqueue(system_highpri_wq);
+       flush_workqueue(wdev->bh_wq);
        start = ktime_get();
        for (;;) {
                wfx_control_reg_read(wdev, ®);
 
        wdev->pdata.gpio_wakeup = NULL;
        wdev->poll_irq = true;
 
+       wdev->bh_wq = alloc_workqueue("wfx_bh_wq", WQ_HIGHPRI, 0);
+       if (!wdev->bh_wq)
+               return -ENOMEM;
+
        wfx_bh_register(wdev);
 
        err = wfx_init_device(wdev);
        wdev->hwbus_ops->irq_unsubscribe(wdev->hwbus_priv);
 bh_unregister:
        wfx_bh_unregister(wdev);
+       destroy_workqueue(wdev->bh_wq);
        return err;
 }
 
        wfx_hif_shutdown(wdev);
        wdev->hwbus_ops->irq_unsubscribe(wdev->hwbus_priv);
        wfx_bh_unregister(wdev);
+       destroy_workqueue(wdev->bh_wq);
 }
 
 static int __init wfx_core_init(void)
 
        struct mutex               rx_stats_lock;
        struct wfx_hif_tx_power_loop_info tx_power_loop_info;
        struct mutex               tx_power_loop_info_lock;
+       struct workqueue_struct    *bh_wq;
 };
 
 struct wfx_vif {