types: move the feature shift/masks from util.h

Signed-off-by: Klaus Jensen <k.jensen@samsung.com>

diff --git a/src/nvme/types.h b/src/nvme/types.h
index f9ccbe1970e4b9ef8a94fc1628c72dbe4d028131..6b0b14716ee6d2bbdc05b163cfde75f367bd5245 100644 (file)
--- a/src/nvme/types.h
+++ b/src/nvme/types.h
@@ -5023,6 +5023,110 @@ enum nvme_features_id {
        NVME_FEAT_FID_WRITE_PROTECT                             = 0x84,
 };
 
+/**
+ * enum nvme_feat -
+ */
+enum nvme_feat {
+       NVME_FEAT_ARBITRATION_BURST_SHIFT       = 0,
+       NVME_FEAT_ARBITRATION_BURST_MASK        = 0x7,
+       NVME_FEAT_ARBITRATION_LPW_SHIFT         = 8,
+       NVME_FEAT_ARBITRATION_LPW_MASK          = 0xff,
+       NVME_FEAT_ARBITRATION_MPW_SHIFT         = 16,
+       NVME_FEAT_ARBITRATION_MPW_MASK          = 0xff,
+       NVME_FEAT_ARBITRATION_HPW_SHIFT         = 24,
+       NVME_FEAT_ARBITRATION_HPW_MASK          = 0xff,
+       NVME_FEAT_PWRMGMT_PS_SHIFT              = 0,
+       NVME_FEAT_PWRMGMT_PS_MASK               = 0x1f,
+       NVME_FEAT_PWRMGMT_WH_SHIFT              = 5,
+       NVME_FEAT_PWRMGMT_WH_MASK               = 0x7,
+       NVME_FEAT_LBAR_NR_SHIFT                 = 0,
+       NVME_FEAT_LBAR_NR_MASK                  = 0x3f,
+       NVME_FEAT_TT_TMPTH_SHIFT                = 0,
+       NVME_FEAT_TT_TMPTH_MASK                 = 0xffff,
+       NVME_FEAT_TT_TMPSEL_SHIFT               = 16,
+       NVME_FEAT_TT_TMPSEL_MASK                = 0xf,
+       NVME_FEAT_TT_THSEL_SHIFT                = 20,
+       NVME_FEAT_TT_THSEL_MASK                 = 0x3,
+       NVME_FEAT_ERROR_RECOVERY_TLER_SHIFT     = 0,
+       NVME_FEAT_ERROR_RECOVERY_TLER_MASK      = 0xffff,
+       NVME_FEAT_ERROR_RECOVERY_DULBE_SHIFT    = 16,
+       NVME_FEAT_ERROR_RECOVERY_DULBE_MASK     = 0x1,
+       NVME_FEAT_VWC_WCE_SHIFT         = 0,
+       NVME_FEAT_VWC_WCE_MASK          = 0x1,
+       NVME_FEAT_NRQS_NSQR_SHIFT       = 0,
+       NVME_FEAT_NRQS_NSQR_MASK        = 0xffff,
+       NVME_FEAT_NRQS_NCQR_SHIFT       = 16,
+       NVME_FEAT_NRQS_NCQR_MASK        = 0xffff,
+       NVME_FEAT_IRQC_THR_SHIFT        = 0,
+       NVME_FEAT_IRQC_THR_MASK = 0xff,
+       NVME_FEAT_IRQC_TIME_SHIFT       = 8,
+       NVME_FEAT_IRQC_TIME_MASK        = 0xff,
+       NVME_FEAT_ICFG_IV_SHIFT         = 0,
+       NVME_FEAT_ICFG_IV_MASK          = 0xffff,
+       NVME_FEAT_ICFG_CD_SHIFT         = 16,
+       NVME_FEAT_ICFG_CD_MASK          = 0x1,
+       NVME_FEAT_WA_DN_SHIFT           = 0,
+       NVME_FEAT_WA_DN_MASK            = 0x1,
+       NVME_FEAT_AE_SMART_SHIFT        = 0,
+       NVME_FEAT_AE_SMART_MASK         = 0xff,
+       NVME_FEAT_AE_NAN_SHIFT          = 8,
+       NVME_FEAT_AE_NAN_MASK           = 0x1,
+       NVME_FEAT_AE_FW_SHIFT           = 9,
+       NVME_FEAT_AE_FW_MASK            = 0x1,
+       NVME_FEAT_AE_TELEM_SHIFT        = 10,
+       NVME_FEAT_AE_TELEM_MASK         = 0x1,
+       NVME_FEAT_AE_ANA_SHIFT          = 11,
+       NVME_FEAT_AE_ANA_MASK           = 0x1,
+       NVME_FEAT_AE_PLA_SHIFT          = 12,
+       NVME_FEAT_AE_PLA_MASK           = 0x1,
+       NVME_FEAT_AE_LBAS_SHIFT         = 13,
+       NVME_FEAT_AE_LBAS_MASK          = 0x1,
+       NVME_FEAT_AE_EGA_SHIFT          = 14,
+       NVME_FEAT_AE_EGA_MASK           = 0x1,
+       NVME_FEAT_APST_APSTE_SHIFT      = 0,
+       NVME_FEAT_APST_APSTE_MASK       = 0x1,
+       NVME_FEAT_HMEM_EHM_SHIFT        = 0,
+       NVME_FEAT_HMEM_EHM_MASK         = 0x1,
+       NVME_FEAT_HCTM_TMT2_SHIFT       = 0,
+       NVME_FEAT_HCTM_TMT2_MASK        = 0xffff,
+       NVME_FEAT_HCTM_TMT1_SHIFT       = 16,
+       NVME_FEAT_HCTM_TMT1_MASK        = 0xffff,
+       NVME_FEAT_NOPS_NOPPME_SHIFT     = 0,
+       NVME_FEAT_NOPS_NOPPME_MASK      = 0x1,
+       NVME_FEAT_RRL_RRL_SHIFT         = 0,
+       NVME_FEAT_RRL_RRL_MASK          = 0xff,
+       NVME_FEAT_PLM_PLME_SHIFT        = 0,
+       NVME_FEAT_PLM_PLME_MASK         = 0x1,
+       NVME_FEAT_PLMW_WS_SHIFT         = 0,
+       NVME_FEAT_PLMW_WS_MASK          = 0x7,
+       NVME_FEAT_LBAS_LSIRI_SHIFT      = 0,
+       NVME_FEAT_LBAS_LSIRI_MASK       = 0xffff,
+       NVME_FEAT_LBAS_LSIPI_SHIFT      = 16,
+       NVME_FEAT_LBAS_LSIPI_MASK       = 0xffff,
+       NVME_FEAT_SC_NODRM_SHIFT        = 0,
+       NVME_FEAT_SC_NODRM_MASK         = 0x1,
+       NVME_FEAT_EG_ENDGID_SHIFT       = 0,
+       NVME_FEAT_EG_ENDGID_MASK        = 0xffff,
+       NVME_FEAT_EG_EGCW_SHIFT         = 16,
+       NVME_FEAT_EG_EGCW_MASK          = 0xff,
+       NVME_FEAT_SPM_PBSLC_SHIFT       = 0,
+       NVME_FEAT_SPM_PBSLC_MASK        = 0xff,
+       NVME_FEAT_HOSTID_EXHID_SHIFT    = 0,
+       NVME_FEAT_HOSTID_EXHID_MASK     = 0x1,
+       NVME_FEAT_RM_REGPRE_SHIFT       = 1,
+       NVME_FEAT_RM_REGPRE_MASK        = 0x1,
+       NVME_FEAT_RM_RESREL_SHIFT       = 2,
+       NVME_FEAT_RM_RESREL_MASK        = 0x1,
+       NVME_FEAT_RM_RESPRE_SHIFT       = 0x3,
+       NVME_FEAT_RM_RESPRE_MASK        = 0x1,
+       NVME_FEAT_RP_PTPL_SHIFT         = 0,
+       NVME_FEAT_RP_PTPL_MASK          = 0x1,
+       NVME_FEAT_WP_WPS_SHIFT          = 0,
+       NVME_FEAT_WP_WPS_MASK           = 0x7,
+       NVME_FEAT_IOCSP_IOCSCI_SHIFT    = 0,
+       NVME_FEAT_IOCSP_IOCSCI_MASK     = 0xff,
+};
+
 /**
  * enum nvme_get_features_sel -
  * @NVME_GET_FEATURES_SEL_CURRENT:

diff --git a/src/nvme/util.h b/src/nvme/util.h
index f4b3b4095efeeb50c9ebf900ff60205697006531..b84ccf7a1f91f00c6651d1c512da709b891dedf1 100644 (file)
--- a/src/nvme/util.h
+++ b/src/nvme/util.h
@@ -262,107 +262,6 @@ static inline void nvme_chomp(char *s, int l)
                s[l--] = '\0';
 }
 
-enum {
-       NVME_FEAT_ARBITRATION_BURST_SHIFT       = 0,
-       NVME_FEAT_ARBITRATION_BURST_MASK        = 0x7,
-       NVME_FEAT_ARBITRATION_LPW_SHIFT         = 8,
-       NVME_FEAT_ARBITRATION_LPW_MASK          = 0xff,
-       NVME_FEAT_ARBITRATION_MPW_SHIFT         = 16,
-       NVME_FEAT_ARBITRATION_MPW_MASK          = 0xff,
-       NVME_FEAT_ARBITRATION_HPW_SHIFT         = 24,
-       NVME_FEAT_ARBITRATION_HPW_MASK          = 0xff,
-       NVME_FEAT_PWRMGMT_PS_SHIFT              = 0,
-       NVME_FEAT_PWRMGMT_PS_MASK               = 0x1f,
-       NVME_FEAT_PWRMGMT_WH_SHIFT              = 5,
-       NVME_FEAT_PWRMGMT_WH_MASK               = 0x7,
-       NVME_FEAT_LBAR_NR_SHIFT                 = 0,
-       NVME_FEAT_LBAR_NR_MASK                  = 0x3f,
-       NVME_FEAT_TT_TMPTH_SHIFT                = 0,
-       NVME_FEAT_TT_TMPTH_MASK                 = 0xffff,
-       NVME_FEAT_TT_TMPSEL_SHIFT               = 16,
-       NVME_FEAT_TT_TMPSEL_MASK                = 0xf,
-       NVME_FEAT_TT_THSEL_SHIFT                = 20,
-       NVME_FEAT_TT_THSEL_MASK                 = 0x3,
-       NVME_FEAT_ERROR_RECOVERY_TLER_SHIFT     = 0,
-       NVME_FEAT_ERROR_RECOVERY_TLER_MASK      = 0xffff,
-       NVME_FEAT_ERROR_RECOVERY_DULBE_SHIFT    = 16,
-       NVME_FEAT_ERROR_RECOVERY_DULBE_MASK     = 0x1,
-       NVME_FEAT_VWC_WCE_SHIFT         = 0,
-       NVME_FEAT_VWC_WCE_MASK          = 0x1,
-       NVME_FEAT_NRQS_NSQR_SHIFT       = 0,
-       NVME_FEAT_NRQS_NSQR_MASK        = 0xffff,
-       NVME_FEAT_NRQS_NCQR_SHIFT       = 16,
-       NVME_FEAT_NRQS_NCQR_MASK        = 0xffff,
-       NVME_FEAT_IRQC_THR_SHIFT        = 0,
-       NVME_FEAT_IRQC_THR_MASK = 0xff,
-       NVME_FEAT_IRQC_TIME_SHIFT       = 8,
-       NVME_FEAT_IRQC_TIME_MASK        = 0xff,
-       NVME_FEAT_ICFG_IV_SHIFT         = 0,
-       NVME_FEAT_ICFG_IV_MASK          = 0xffff,
-       NVME_FEAT_ICFG_CD_SHIFT         = 16,
-       NVME_FEAT_ICFG_CD_MASK          = 0x1,
-       NVME_FEAT_WA_DN_SHIFT           = 0,
-       NVME_FEAT_WA_DN_MASK            = 0x1,
-       NVME_FEAT_AE_SMART_SHIFT        = 0,
-       NVME_FEAT_AE_SMART_MASK         = 0xff,
-       NVME_FEAT_AE_NAN_SHIFT          = 8,
-       NVME_FEAT_AE_NAN_MASK           = 0x1,
-       NVME_FEAT_AE_FW_SHIFT           = 9,
-       NVME_FEAT_AE_FW_MASK            = 0x1,
-       NVME_FEAT_AE_TELEM_SHIFT        = 10,
-       NVME_FEAT_AE_TELEM_MASK         = 0x1,
-       NVME_FEAT_AE_ANA_SHIFT          = 11,
-       NVME_FEAT_AE_ANA_MASK           = 0x1,
-       NVME_FEAT_AE_PLA_SHIFT          = 12,
-       NVME_FEAT_AE_PLA_MASK           = 0x1,
-       NVME_FEAT_AE_LBAS_SHIFT         = 13,
-       NVME_FEAT_AE_LBAS_MASK          = 0x1,
-       NVME_FEAT_AE_EGA_SHIFT          = 14,
-       NVME_FEAT_AE_EGA_MASK           = 0x1,
-       NVME_FEAT_APST_APSTE_SHIFT      = 0,
-       NVME_FEAT_APST_APSTE_MASK       = 0x1,
-       NVME_FEAT_HMEM_EHM_SHIFT        = 0,
-       NVME_FEAT_HMEM_EHM_MASK         = 0x1,
-       NVME_FEAT_HCTM_TMT2_SHIFT       = 0,
-       NVME_FEAT_HCTM_TMT2_MASK        = 0xffff,
-       NVME_FEAT_HCTM_TMT1_SHIFT       = 16,
-       NVME_FEAT_HCTM_TMT1_MASK        = 0xffff,
-       NVME_FEAT_NOPS_NOPPME_SHIFT     = 0,
-       NVME_FEAT_NOPS_NOPPME_MASK      = 0x1,
-       NVME_FEAT_RRL_RRL_SHIFT         = 0,
-       NVME_FEAT_RRL_RRL_MASK          = 0xff,
-       NVME_FEAT_PLM_PLME_SHIFT        = 0,
-       NVME_FEAT_PLM_PLME_MASK         = 0x1,
-       NVME_FEAT_PLMW_WS_SHIFT         = 0,
-       NVME_FEAT_PLMW_WS_MASK          = 0x7,
-       NVME_FEAT_LBAS_LSIRI_SHIFT      = 0,
-       NVME_FEAT_LBAS_LSIRI_MASK       = 0xffff,
-       NVME_FEAT_LBAS_LSIPI_SHIFT      = 16,
-       NVME_FEAT_LBAS_LSIPI_MASK       = 0xffff,
-       NVME_FEAT_SC_NODRM_SHIFT        = 0,
-       NVME_FEAT_SC_NODRM_MASK         = 0x1,
-       NVME_FEAT_EG_ENDGID_SHIFT       = 0,
-       NVME_FEAT_EG_ENDGID_MASK        = 0xffff,
-       NVME_FEAT_EG_EGCW_SHIFT         = 16,
-       NVME_FEAT_EG_EGCW_MASK          = 0xff,
-       NVME_FEAT_SPM_PBSLC_SHIFT       = 0,
-       NVME_FEAT_SPM_PBSLC_MASK        = 0xff,
-       NVME_FEAT_HOSTID_EXHID_SHIFT    = 0,
-       NVME_FEAT_HOSTID_EXHID_MASK     = 0x1,
-       NVME_FEAT_RM_REGPRE_SHIFT       = 1,
-       NVME_FEAT_RM_REGPRE_MASK        = 0x1,
-       NVME_FEAT_RM_RESREL_SHIFT       = 2,
-       NVME_FEAT_RM_RESREL_MASK        = 0x1,
-       NVME_FEAT_RM_RESPRE_SHIFT       = 0x3,
-       NVME_FEAT_RM_RESPRE_MASK        = 0x1,
-       NVME_FEAT_RP_PTPL_SHIFT         = 0,
-       NVME_FEAT_RP_PTPL_MASK          = 0x1,
-       NVME_FEAT_WP_WPS_SHIFT          = 0,
-       NVME_FEAT_WP_WPS_MASK           = 0x7,
-       NVME_FEAT_IOCSP_IOCSCI_SHIFT    = 0,
-       NVME_FEAT_IOCSP_IOCSCI_MASK     = 0xff,
-};
-
 #define NVME_FEAT_ARB_BURST(v)         NVME_GET(v, FEAT_ARBITRATION_BURST)
 #define NVME_FEAT_ARB_LPW(v)           NVME_GET(v, FEAT_ARBITRATION_LPW)
 #define NVME_FEAT_ARB_MPW(v)           NVME_GET(v, FEAT_ARBITRATION_MPW)