i3c: mipi-i3c-hci: Allow only relevant INTR_STATUS bit updates

Since MIPI I3C HCI specification version v0.8 INTR_STATUS bits 9:0 are
reserved. Version v0.5 has bits 9 and 5:0 in use but not handled by the
current driver code and not needed in DMA transfers.

PIO transfers with v0.5 would require changes to both
core.c: i3c_hci_irq_handler() and pio.c: hci_pio_irq_handler() though.

For these reasons don't enable signal updates from INTR_STATUS bits 9:0.

It allow to get rid of "unexpected INTR_STATUS" error messages on old
v0.5 IP version and is a no-op for later versions starting from v0.8.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250409140401.299251-1-jarkko.nikula@linux.intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index a71226d7ca59328f626ddcf6f590c4232025dc17..ba7aa6bbcec5f78d23958e0de329f0c59ac34089 100644 (file)
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -699,9 +699,14 @@ static int i3c_hci_init(struct i3c_hci *hci)
        if (ret)
                return -ENXIO;
 
-       /* Disable all interrupts and allow all signal updates */
+       /* Disable all interrupts */
        reg_write(INTR_SIGNAL_ENABLE, 0x0);
-       reg_write(INTR_STATUS_ENABLE, 0xffffffff);
+       /*
+        * Only allow bit 31:10 signal updates because
+        * Bit 0:9 are reserved in IP version >= 0.8
+        * Bit 0:5 are defined in IP version < 0.8 but not handled by PIO code
+        */
+       reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
 
        /* Make sure our data ordering fits the host's */
        regval = reg_read(HC_CONTROL);