ARM: dts: r8a7792: add JPU clocks

Add JPU clock and its parent, M2 clock to the R8A7792 device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 18b4e50521c3033eccfdaa068cd709213bc2b39d..7077c5db2678c32a249b8a783ae3efdee77602df 100644 (file)
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -280,8 +280,24 @@
                        clock-div = <48>;
                        clock-mult = <1>;
                };
+               m2_clk: m2 {
+                       compatible = "fixed-factor-clock";
+                       clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+                       #clock-cells = <0>;
+                       clock-div = <8>;
+                       clock-mult = <1>;
+               };
 
                /* Gate clocks */
+               mstp1_clks: mstp1_clks@e6150134 {
+                       compatible = "renesas,r8a7792-mstp-clocks",
+                                    "renesas,cpg-mstp-clocks";
+                       reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+                       clocks = <&m2_clk>;
+                       #clock-cells = <1>;
+                       clock-indices = <R8A7792_CLK_JPU>;
+                       clock-output-names = "jpu";
+               };
                mstp2_clks: mstp2_clks@e6150138 {
                        compatible = "renesas,r8a7792-mstp-clocks",
                                     "renesas,cpg-mstp-clocks";

diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h
index 949801eb065220587900c21a34c0c729c27e0678..89a5155913f6f127a829c334d90992d1aa87b735 100644 (file)
--- a/include/dt-bindings/clock/r8a7792-clock.h
+++ b/include/dt-bindings/clock/r8a7792-clock.h
@@ -24,6 +24,7 @@
 #define R8A7792_CLK_MSIOF0             0
 
 /* MSTP1 */
+#define R8A7792_CLK_JPU                        6
 #define R8A7792_CLK_TMU1               11
 #define R8A7792_CLK_TMU3               21
 #define R8A7792_CLK_TMU2               22