if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
                pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
 
-       tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
-       tmp &= ~EXYNOS5_USE_RETENTION;
-       pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
+       tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
+       tmp &= ~EXYNOS_L2_USE_RETENTION;
+       pmu_raw_writel(tmp, EXYNOS_L2_OPTION(0));
 
        tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
        tmp |= EXYNOS5420_UFS;
 
        { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
        { EXYNOS5_ARM_COMMON_SYS_PWR_REG,               { 0x0, 0x0, 0x2} },
        { EXYNOS5_ARM_L2_SYS_PWR_REG,                   { 0x3, 0x3, 0x3} },
-       { EXYNOS5_ARM_L2_OPTION,                        { 0x10, 0x10, 0x0 } },
+       { EXYNOS_L2_OPTION(0),                          { 0x10, 0x10, 0x0 } },
        { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
        { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
        { EXYNOS5_CMU_RESET_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
 
        pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
 
        value  = pmu_raw_readl(EXYNOS_L2_OPTION(0));
-       value &= ~EXYNOS5_USE_RETENTION;
+       value &= ~EXYNOS_L2_USE_RETENTION;
        pmu_raw_writel(value, EXYNOS_L2_OPTION(0));
 
        value = pmu_raw_readl(EXYNOS_L2_OPTION(1));
-       value &= ~EXYNOS5_USE_RETENTION;
+       value &= ~EXYNOS_L2_USE_RETENTION;
        pmu_raw_writel(value, EXYNOS_L2_OPTION(1));
 
        /*
 
 #define EXYNOS_L2_OPTION(_nr)                  \
                        (EXYNOS_L2_CONFIGURATION(_nr) + 0x8)
 
-#define EXYNOS5_ARM_L2_OPTION                  0x2608
-#define EXYNOS5_USE_RETENTION                  BIT(4)
+#define EXYNOS_L2_USE_RETENTION                        BIT(4)
 
 #define S5P_PAD_RET_MAUDIO_OPTION              0x3028
 #define S5P_PAD_RET_MMC2_OPTION                        0x30c8