clk: qcom: clk-alpha-pll: Refactor trion PLL

Remove duplicate function for calculating the round rate of PLL and also
update the trion pll ops to use the common function.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20200224045003.3783838-3-vkoul@kernel.org
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 0bdf6e45fac9fdf5f335a97ba9f4d63da8f6f3bb..0adec585eb4fba603e36419efbeecea82b958485 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -845,33 +845,12 @@ static unsigned long
 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 {
        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
-       struct regmap *regmap = pll->clkr.regmap;
-       u32 l, frac;
-       u64 prate = parent_rate;
-
-       regmap_read(regmap, PLL_L_VAL(pll), &l);
-       regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
-
-       return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
-}
-
-static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
-                                    unsigned long *prate)
-{
-       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
-       unsigned long min_freq, max_freq;
-       u32 l;
-       u64 a;
-
-       rate = alpha_pll_round_rate(rate, *prate,
-                                   &l, &a, ALPHA_REG_16BIT_WIDTH);
-       if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
-               return rate;
+       u32 l, frac, alpha_width = pll_alpha_width(pll);
 
-       min_freq = pll->vco_table[0].min_freq;
-       max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
+       regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
+       regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
 
-       return clamp(rate, min_freq, max_freq);
+       return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
 }
 
 const struct clk_ops clk_alpha_pll_fixed_ops = {
@@ -917,7 +896,7 @@ const struct clk_ops clk_trion_fixed_pll_ops = {
        .disable = clk_trion_pll_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = clk_trion_pll_recalc_rate,
-       .round_rate = clk_trion_pll_round_rate,
+       .round_rate = clk_alpha_pll_round_rate,
 };
 EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
 
@@ -1173,7 +1152,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
         * Due to limited number of bits for fractional rate programming, the
         * rounded up rate could be marginally higher than the requested rate.
         */
-       if (rrate > max || rrate < rate) {
+       if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
                pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
                       clk_hw_get_name(hw), rrate, rate, max);
                return -EINVAL;