static void qm_hw_error_init_v1(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
                                u32 msi)
 {
-       dev_info(&qm->pdev->dev,
-                "QM v%d does not support hw error handle\n", qm->ver);
-
        writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
 }
 
                           u32 msi)
 {
        if (!qm->ops->hw_error_init) {
-               dev_err(&qm->pdev->dev, "QM version %d doesn't support hw error handling!\n",
-                       qm->ver);
+               dev_err(&qm->pdev->dev, "QM doesn't support hw error handling!\n");
                return;
        }
 
 int hisi_qm_hw_error_handle(struct hisi_qm *qm)
 {
        if (!qm->ops->hw_error_handle) {
-               dev_err(&qm->pdev->dev, "QM version %d doesn't support hw error report!\n",
-                       qm->ver);
+               dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n");
                return PCI_ERS_RESULT_NONE;
        }
 
 
 
        if (qm->ver == QM_HW_V1) {
                writel(HZIP_CORE_INT_DISABLE, qm->io_base + HZIP_CORE_INT_MASK);
-               dev_info(&qm->pdev->dev, "ZIP v%d does not support hw error handle\n",
-                        qm->ver);
+               dev_info(&qm->pdev->dev, "Does not support hw error handle\n");
                return;
        }