]> www.infradead.org Git - linux.git/commitdiff
perf arm-spe: Correctly set sample flags
authorGraham Woodward <graham.woodward@arm.com>
Fri, 25 Oct 2024 14:30:08 +0000 (15:30 +0100)
committerNamhyung Kim <namhyung@kernel.org>
Tue, 29 Oct 2024 23:10:14 +0000 (16:10 -0700)
Set flags on all synthesized instruction and branch samples.

Signed-off-by: Graham Woodward <graham.woodward@arm.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Tested-by: Leo Yan <leo.yan@arm.com>
Cc: nd@arm.com
Cc: mike.leach@linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20241025143009.25419-4-graham.woodward@arm.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
tools/perf/builtin-script.c
tools/perf/util/arm-spe.c
tools/perf/util/event.h

index 8c5d5cecfba489ce79537c0d78086b47f6bc54c0..6b6d4472db6e61c0d7dbf955b5dba18172d9b003 100644 (file)
@@ -1728,6 +1728,7 @@ static struct {
        {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TRACE_END, "tr end"},
        {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | PERF_IP_FLAG_VMENTRY, "vmentry"},
        {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | PERF_IP_FLAG_VMEXIT, "vmexit"},
+       {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_BRANCH_MISS, "br miss"},
        {0, NULL}
 };
 
index e60e21d247355ea3f84845da21749dbdde6f7f74..a291a412f6a142ee54c0674165846efb13242ece 100644 (file)
@@ -100,6 +100,7 @@ struct arm_spe_queue {
        u64                             timestamp;
        struct thread                   *thread;
        u64                             period_instructions;
+       u32                             flags;
 };
 
 static void arm_spe_dump(struct arm_spe *spe __maybe_unused,
@@ -394,6 +395,7 @@ static int arm_spe__synth_branch_sample(struct arm_spe_queue *speq,
        sample.stream_id = spe_events_id;
        sample.addr = record->to_ip;
        sample.weight = record->latency;
+       sample.flags = speq->flags;
 
        return arm_spe_deliver_synth_event(spe, speq, event, &sample);
 }
@@ -423,6 +425,7 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq,
        sample.data_src = data_src;
        sample.period = spe->instructions_sample_period;
        sample.weight = record->latency;
+       sample.flags = speq->flags;
 
        return arm_spe_deliver_synth_event(spe, speq, event, &sample);
 }
@@ -440,6 +443,19 @@ static const struct midr_range common_ds_encoding_cpus[] = {
        {},
 };
 
+static void arm_spe__sample_flags(struct arm_spe_queue *speq)
+{
+       const struct arm_spe_record *record = &speq->decoder->record;
+
+       speq->flags = 0;
+       if (record->op & ARM_SPE_OP_BRANCH_ERET) {
+               speq->flags = PERF_IP_FLAG_BRANCH;
+
+               if (record->type & ARM_SPE_BRANCH_MISS)
+                       speq->flags |= PERF_IP_FLAG_BRANCH_MISS;
+       }
+}
+
 static void arm_spe__synth_data_source_common(const struct arm_spe_record *record,
                                              union perf_mem_data_src *data_src)
 {
@@ -622,6 +638,7 @@ static int arm_spe_sample(struct arm_spe_queue *speq)
        u64 data_src;
        int err;
 
+       arm_spe__sample_flags(speq);
        data_src = arm_spe__synth_data_source(speq, record);
 
        if (spe->sample_flc) {
index f8742e6230a5ab0cbcd8e2fa8d04fefb70767780..2744c54f404e7b3502e2a5d6f17f9c6a133a7b05 100644 (file)
@@ -66,6 +66,7 @@ enum {
        PERF_IP_FLAG_VMEXIT             = 1ULL << 12,
        PERF_IP_FLAG_INTR_DISABLE       = 1ULL << 13,
        PERF_IP_FLAG_INTR_TOGGLE        = 1ULL << 14,
+       PERF_IP_FLAG_BRANCH_MISS        = 1ULL << 15,
 };
 
 #define PERF_IP_FLAG_CHARS "bcrosyiABExghDt"