drm/amdgpu: value of amdgpu_sriov_vf cannot be set into F32_POLL_ENABLE

amdgpu_sriov_vf would return 0x0 or 0x4 to indicate if sriov.
but F32_POLL_ENABLE need 0x0 or 0x1 to determine if enabled.
set 0x4 into F32_POLL_ENABLE would make SDMA0_GFX_RB_WPTR_POLL_CNTL not working.

Signed-off-by: Wentao Lou <Wentao.Lou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 348249185fb26b6d6c33c1c6c07c3ae8f82f4b66..9c88ce513d78e98642522f77820ed224a43fde5b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -849,7 +849,7 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
        wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
        wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
                                       SDMA0_GFX_RB_WPTR_POLL_CNTL,
-                                      F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
+                                      F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
        WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 
        /* enable DMA RB */
@@ -940,7 +940,7 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
        wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
        wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
                                       SDMA0_PAGE_RB_WPTR_POLL_CNTL,
-                                      F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
+                                      F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
        WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 
        /* enable DMA RB */