clk: ingenic: Fix bugs with divided dividers

Two fixes in one:

- In the "impose hardware constraints" block, the "logical" divider
  value (aka. not translated to the hardware) was clamped to fit in the
  register area, but this totally ignored the fact that the divider
  value can itself have a fixed divider.

- The code that made sure that the divider value returned by the
  function was a multiple of its own fixed divider could result in a
  wrong value being calculated, because it was rounded down instead of
  rounded up.

Fixes: 4afe2d1a6ed5 ("clk: ingenic: Allow divider value to be divided")
Co-developed-by: Artur Rojek <contact@artur-rojek.eu>
Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20211001172033.122329-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 266c7595d33022878b05a208bc4000258d61e466..af31633a8862e18f7e20bd25ad3b916713ae831c 100644 (file)
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -453,15 +453,15 @@ ingenic_clk_calc_div(struct clk_hw *hw,
        }
 
        /* Impose hardware constraints */
-       div = min_t(unsigned, div, 1 << clk_info->div.bits);
-       div = max_t(unsigned, div, 1);
+       div = clamp_t(unsigned int, div, clk_info->div.div,
+                     clk_info->div.div << clk_info->div.bits);
 
        /*
         * If the divider value itself must be divided before being written to
         * the divider register, we must ensure we don't have any bits set that
         * would be lost as a result of doing so.
         */
-       div /= clk_info->div.div;
+       div = DIV_ROUND_UP(div, clk_info->div.div);
        div *= clk_info->div.div;
 
        return div;