KVM: arm64: Always support SW_INCR PMU event

Support for SW_INCR is unconditional, as KVM traps accesses to
PMSWINC_EL0 and emulates the intended event increment. While it is
expected that ~all PMUv3 implementations already advertise this event,
non-PMUv3 hardware may not.

Tested-by: Janne Grunau <j@jannau.net>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250305202641.428114-5-oliver.upton@linux.dev
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index 104672a0c5a21bf415cc932b8904cb92c321f5c4..62349b670cf92b849bb14868e275002b17cd239b 100644 (file)
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -856,6 +856,8 @@ static u64 compute_pmceid0(struct arm_pmu *pmu)
 {
        u64 val = __compute_pmceid(pmu, 0);
 
+       /* always support SW_INCR */
+       val |= BIT(ARMV8_PMUV3_PERFCTR_SW_INCR);
        /* always support CHAIN */
        val |= BIT(ARMV8_PMUV3_PERFCTR_CHAIN);
        return val;