x86/cpufeatures: Add detection of L1D cache flush support.

336996-Speculative-Execution-Side-Channel-Mitigations.pdf defines a new MSR
(IA32_FLUSH_CMD) which is detected by CPUID.7.EDX[28]=1 bit being set.

This new MSR "gives software a way to invalidate structures with finer
granularity than other architectual methods like WBINVD."

A copy of this document is available at
  https://bugzilla.kernel.org/show_bug.cgi?id=199511

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Orabug: 28220674
CVE: CVE-2018-3620

(cherry picked from commit 11e34e64e4103955fc4568750914c75d65ea87ee)

Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Conflicts:
	arch/x86/include/asm/cpufeatures.h
We do not have word 18. To preserve kABI compat we will use word 2 which has
free entries.

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 684f044c90b9f5b95c808e3de3f38dc04e681ecc..c6a4944caefaf2bd349fb40b146845e3f05ab4a7 100644 (file)
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -72,6 +72,7 @@
  * in various CPUID levels like 0x6, 0xA etc, word 2
  */
 #define X86_FEATURE_L1TF_PTEINV                ( 2*32+0) /* "" L1TF workaround PTE inversion */
+#define X86_FEATURE_FLUSH_L1D          ( 2*32+1) /* Flush L1D cache */
 
 /* Other features, Linux-defined mapping, word 3 */
 /* This range is used for feature bits which conflict or are synthesized */

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 598c2a9cc149d2c5eac71dcf0846120175b93cb0..af750592a001a7f33e9f542e54d64b8cc24464c2 100644 (file)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -697,6 +697,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c, enum get_cpu_cap_behavior behavior)
                cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
 
                c->x86_capability[9] = ebx;
+
+               if (edx & BIT(28))
+                       set_cpu_cap(c, X86_FEATURE_FLUSH_L1D);
        }
 
        /* Extended state features: level 0x0000000d */