]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
brcmfmac: Add BCM43454/6 support
authorZhao, Jiaqing <jiaqing.zhao@intel.com>
Wed, 9 Feb 2022 15:46:50 +0000 (15:46 +0000)
committerKalle Valo <kvalo@kernel.org>
Mon, 14 Feb 2022 18:05:24 +0000 (20:05 +0200)
BCM43454/6 is a variant of BCM4345 which is exactly identical to
BCM4345/6, except the chip id is 0xa9be. This patch adds support
for BCM43454/6 by handing it in the same way as BCM4345.

Note: when loading some specific version of BCM4345 firmware, the
chip id may become 0x4345. This is an expected behavior, and it will
restore to 0xa9be after power cycle.

Signed-off-by: Jiaqing Zhao <jiaqing.zhao@intel.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/CO1PR11MB47859B51BCA88613D1582EB88E2E9@CO1PR11MB4785.namprd11.prod.outlook.com
drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h

index 1ee49f9e325dbf72c68952eb2071ba17d6c4aafe..4ec7773b690645daef40307e7d5d06c95da47c5d 100644 (file)
@@ -704,6 +704,7 @@ static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
 {
        switch (ci->pub.chip) {
        case BRCM_CC_4345_CHIP_ID:
+       case BRCM_CC_43454_CHIP_ID:
                return 0x198000;
        case BRCM_CC_4335_CHIP_ID:
        case BRCM_CC_4339_CHIP_ID:
@@ -1401,6 +1402,7 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
        case BRCM_CC_4354_CHIP_ID:
        case BRCM_CC_4356_CHIP_ID:
        case BRCM_CC_4345_CHIP_ID:
+       case BRCM_CC_43454_CHIP_ID:
                /* explicitly check SR engine enable bit */
                pmu_cc3_mask = BIT(2);
                fallthrough;
index 7c68d98493246c45c1ef73ab5f34fd7c4f789cd8..d2ac844e1e9ffe3f1111eaf945903a3f1e7dfe24 100644 (file)
@@ -248,7 +248,8 @@ void brcmf_feat_attach(struct brcmf_pub *drvr)
        brcmf_feat_firmware_capabilities(ifp);
        memset(&gscan_cfg, 0, sizeof(gscan_cfg));
        if (drvr->bus_if->chip != BRCM_CC_43430_CHIP_ID &&
-           drvr->bus_if->chip != BRCM_CC_4345_CHIP_ID)
+           drvr->bus_if->chip != BRCM_CC_4345_CHIP_ID &&
+           drvr->bus_if->chip != BRCM_CC_43454_CHIP_ID)
                brcmf_feat_iovar_data_set(ifp, BRCMF_FEAT_GSCAN,
                                          "pfn_gscan_cfg",
                                          &gscan_cfg, sizeof(gscan_cfg));
index 5d156e591b35ccfcd2e9e33fbc8fd8fa3b607cfe..ba3c159111d3155c0475385bfc43e063a303c286 100644 (file)
@@ -651,6 +651,7 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
        BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFC, 43430B0),
        BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456),
        BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455),
+       BRCMF_FW_ENTRY(BRCM_CC_43454_CHIP_ID, 0x00000040, 43455),
        BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
        BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
        BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
index 3bbe2388ec54a23d1e409208b8ae003639095e9b..ed0b707f0cdfc4ac5e00fc40a5950db745160e1a 100644 (file)
@@ -32,6 +32,7 @@
 #define BRCM_CC_4339_CHIP_ID           0x4339
 #define BRCM_CC_43430_CHIP_ID          43430
 #define BRCM_CC_4345_CHIP_ID           0x4345
+#define BRCM_CC_43454_CHIP_ID          43454
 #define BRCM_CC_43465_CHIP_ID          43465
 #define BRCM_CC_4350_CHIP_ID           0x4350
 #define BRCM_CC_43525_CHIP_ID          43525