return hba->ufs_version;
 }
 
+#define MAX_VCC_NAME 30
+static int ufs_mtk_vreg_fix_vcc(struct ufs_hba *hba)
+{
+       struct ufs_vreg_info *info = &hba->vreg_info;
+       struct device_node *np = hba->dev->of_node;
+       struct device *dev = hba->dev;
+       char vcc_name[MAX_VCC_NAME];
+       struct arm_smccc_res res;
+       int err, ver;
+
+       if (hba->vreg_info.vcc)
+               return 0;
+
+       if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) {
+               ufs_mtk_get_vcc_num(res);
+               if (res.a1 > UFS_VCC_NONE && res.a1 < UFS_VCC_MAX)
+                       snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%u", res.a1);
+               else
+                       return -ENODEV;
+       } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) {
+               ver = (hba->dev_info.wspecversion & 0xF00) >> 8;
+               snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver);
+       } else {
+               return 0;
+       }
+
+       err = ufshcd_populate_vreg(dev, vcc_name, &info->vcc);
+       if (err)
+               return err;
+
+       err = ufshcd_get_vreg(dev, info->vcc);
+       if (err)
+               return err;
+
+       err = regulator_enable(info->vcc->reg);
+       if (!err) {
+               info->vcc->enabled = true;
+               dev_info(dev, "%s: %s enabled\n", __func__, vcc_name);
+       }
+
+       return err;
+}
+
 /**
  * ufs_mtk_init - find other essential mmio bases
  * @hba: host controller instance
        else
                ufs_mtk_setup_ref_clk_wait_us(hba,
                                              REFCLK_DEFAULT_WAIT_US);
-
        return 0;
 }
 
                hba->dev_quirks &= ~(UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
                        UFS_DEVICE_QUIRK_DELAY_AFTER_LPM);
        }
+
+       ufs_mtk_vreg_fix_vcc(hba);
 }
 
 static void ufs_mtk_event_notify(struct ufs_hba *hba,
 
 #define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
 #define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
 #define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
+#define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
 #define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
 
 /*
        u32 ip_ver;
 };
 
+/*
+ * Multi-VCC by Numbering
+ */
+enum ufs_mtk_vcc_num {
+       UFS_VCC_NONE = 0,
+       UFS_VCC_1,
+       UFS_VCC_2,
+       UFS_VCC_MAX
+};
+
 /*
  * SMC call wrapper function
  */
 #define ufs_mtk_device_reset_ctrl(high, res) \
        ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
 
+#define ufs_mtk_get_vcc_num(res) \
+       ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
+
 #define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \
        ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver)