arm64: Add work around for Arm Cortex-A55 Erratum 1024718

Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table entry is modified without a break-before-make
sequence. The work around is to skip enabling the hardware DBM feature
on the affected cores. The hardware Access Flag management features
is not affected. There are some other cores suffering from this
errata, which could be added to the midr_list to trigger the work
around.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: ckadabi@codeaurora.org
Reviewed-by: Dave Martin <dave.martin@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index c1d520de6dfebd839b8496dbd1bd65164010bcf6..3b2f2dd82225aee697cc1b6baa1fcbd0092094a2 100644 (file)
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -55,6 +55,7 @@ stable kernels.
 | ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220        |
 | ARM            | Cortex-A72      | #853709         | N/A                         |
 | ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |
+| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |
 | ARM            | MMU-500         | #841119,#826419 | N/A                         |
 |                |                 |                 |                             |
 | Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a6688fcf3dc6a6bfc9957b7b2cca15ffb7b22dae..fd74c58302328cacca2e6ce636b0df3a10069d74 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -465,6 +465,20 @@ config ARM64_ERRATUM_843419
 
          If unsure, say Y.
 
+config ARM64_ERRATUM_1024718
+       bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
+       default y
+       help
+         This option adds work around for Arm Cortex-A55 Erratum 1024718.
+
+         Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
+         update of the hardware dirty bit when the DBM/AP bits are updated
+         without a break-before-make. The work around is to disable the usage
+         of hardware DBM locally on the affected cores. CPUs not affected by
+         erratum will continue to use the feature.
+
+         If unsure, say Y.
+
 config CAVIUM_ERRATUM_22375
        bool "Cavium erratum 22375, 24313"
        default y

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 35e7ae8967f368b7c795f5aa7b0af4f2c940c0b8..381bb4077563f8a197e896c57b6942b6581ec2c8 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -966,9 +966,23 @@ static inline void __cpu_enable_hw_dbm(void)
        isb();
 }
 
+static bool cpu_has_broken_dbm(void)
+{
+       /* List of CPUs which have broken DBM support. */
+       static const struct midr_range cpus[] = {
+#ifdef CONFIG_ARM64_ERRATUM_1024718
+               MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
+#endif
+               {},
+       };
+
+       return is_midr_in_range_list(read_cpuid_id(), cpus);
+}
+
 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
 {
-       return has_cpuid_feature(cap, SCOPE_LOCAL_CPU);
+       return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
+              !cpu_has_broken_dbm();
 }
 
 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)