mtd: nand: sunxi: let the NAND controller control the CE line

We don't need to manually toggle the CE line since the controller handles
it for us. Moreover, keeping the CE line low when interacting with a DDR
NAND can be problematic (data loss in some corner cases).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index ab572dd5ad3cb706f2b31e0e2b8869f88767f738..4dcc0e42e0effba169cb2e1c35378881cb2352fb 100644 (file)
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -514,21 +514,11 @@ static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
        struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
        struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
        int ret;
-       u32 tmp;
 
        ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
        if (ret)
                return;
 
-       if (ctrl & NAND_CTRL_CHANGE) {
-               tmp = readl(nfc->regs + NFC_REG_CTL);
-               if (ctrl & NAND_NCE)
-                       tmp |= NFC_CE_CTL;
-               else
-                       tmp &= ~NFC_CE_CTL;
-               writel(tmp, nfc->regs + NFC_REG_CTL);
-       }
-
        if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
            !(ctrl & (NAND_CLE | NAND_ALE))) {
                u32 cmd = 0;