might_sleep();
 
        memset(&flush_cmd, 0, sizeof(flush_cmd));
-       flush_cmd.fifo_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK |
+       if (flush_control & BIT(IWL_RXON_CTX_BSS))
+               flush_cmd.fifo_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK |
                                 IWL_SCD_BE_MSK | IWL_SCD_BK_MSK |
                                 IWL_SCD_MGMT_MSK;
-       if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
+       if ((flush_control & BIT(IWL_RXON_CTX_PAN)) &&
+           (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)))
                flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK |
                                IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK |
                                IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK |
 
 #define IWL_AGG_TX_QUEUE_MSK           cpu_to_le32(0xffc00)
 
 #define IWL_DROP_SINGLE                0
-#define IWL_DROP_SELECTED      1
-#define IWL_DROP_ALL           2
+#define IWL_DROP_ALL           (BIT(IWL_RXON_CTX_BSS) | BIT(IWL_RXON_CTX_PAN))
 
 /*
  * REPLY_TXFIFO_FLUSH = 0x1e(command and response)