{
        struct drm_plane_state  *state  = plane->state;
        u32 reg;
-       int ret;
        s64 gpu_addr = 0;
        unsigned int line_l;
        struct hibmc_drm_private *priv = plane->dev->dev_private;
        hibmc_fb = to_hibmc_framebuffer(state->fb);
        gbo = drm_gem_vram_of_gem(hibmc_fb->obj);
 
-       ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM);
-       if (ret) {
-               DRM_ERROR("failed to pin bo: %d", ret);
-               return;
-       }
        gpu_addr = drm_gem_vram_offset(gbo);
-       if (gpu_addr < 0) {
-               drm_gem_vram_unpin(gbo);
-               return;
-       }
+       if (WARN_ON_ONCE(gpu_addr < 0))
+               return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */
 
        writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
 
 };
 
 static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = {
+       .prepare_fb     = drm_gem_vram_plane_helper_prepare_fb,
+       .cleanup_fb     = drm_gem_vram_plane_helper_cleanup_fb,
        .atomic_check = hibmc_plane_atomic_check,
        .atomic_update = hibmc_plane_atomic_update,
 };