drm/xe/xe2: Add performance turning changes

Update performance tuning according to the hardware spec.

Bspec: 72161
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240805053710.877119-1-shekhar.chauhan@intel.com

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index c50643ab4c844ffef9ad086e992f8c5de771b331..2c8c4d4218dbe5bebc209e9180c3e01cf6dbbb22 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -80,6 +80,9 @@
 #define   LE_CACHEABILITY_MASK                 REG_GENMASK(1, 0)
 #define   LE_CACHEABILITY(value)               REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
 
+#define STATELESS_COMPRESSION_CTRL             XE_REG(0x4148)
+#define   UNIFIED_COMPRESSION_FORMAT           REG_GENMASK(3, 0)
+
 #define XE2_GAMREQSTRM_CTRL                    XE_REG(0x4194)
 #define   CG_DIS_CNTLBUS                       REG_BIT(6)
 
@@ -193,6 +196,7 @@
 #define GSCPSMI_BASE                           XE_REG(0x880c)
 
 #define CCCHKNREG1                             XE_REG_MCR(0x8828)
+#define   L3CMPCTRL                            REG_BIT(23)
 #define   ENCOMPPERFFIX                                REG_BIT(18)
 
 /* Fuse readout registers for GT */

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 3817b7743b0ca452b04a3383aa0fcda6d915e995..faa1bf42e50edf7011060ae21a3d827ed02cd6b3 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -39,7 +39,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
        },
        { XE_RTP_NAME("Tuning: Compression Overfetch"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
-         XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX)),
+         XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
+                        SET(CCCHKNREG1, L3CMPCTRL))
        },
        { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
@@ -50,6 +51,11 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
          XE_RTP_ACTIONS(SET(L3SQCREG2,
                             COMPMEMRD256BOVRFETCHEN))
        },
+       { XE_RTP_NAME("Tuning: Stateless compression control"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+         XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
+                                  REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
+       },
        {}
 };