arm64: errata: Unify speculative SSBS errata logic

Cortex-X4 erratum 3194386 and Neoverse-V3 erratum 3312417 are identical,
with duplicate Kconfig text and some unsightly ifdeffery. While we try
to share code behind CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS, having
separate options results in a fair amount of boilerplate code, and this
will only get worse as we expand the set of affected CPUs.

To reduce this boilerplate, unify the two behind a common Kconfig
option. This removes the duplicate text and Kconfig logic, and removes
the need for the intermediate ARM64_WORKAROUND_SPECULATIVE_SSBS option.
The set of affected CPUs is described as a list so that this can easily
be extended.

I've used ARM64_ERRATUM_3194386 (matching the Neoverse-V3 erratum ID) as
the common option, matching the way we use ARM64_ERRATUM_1319367 to
cover Cortex-A57 erratum 1319537 and Cortex-A72 erratum 1319367.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <wilL@kernel.org>
Link: https://lore.kernel.org/r/20240603111812.1514101-5-mark.rutland@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index eb8af8032c3156bae5eec2036c127a882d62baac..59ee2832406c292d514238f0cc2276b37809d331 100644 (file)
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -158,7 +158,7 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V1     | #1619801        | N/A                         |
 +----------------+-----------------+-----------------+-----------------------------+
-| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3312417       |
+| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | MMU-500         | #841119,826419  | N/A                         |
 +----------------+-----------------+-----------------+-----------------------------+

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 5d91259ee7b53a36f32b84512706c9f9a09d6620..fb31ff9151b9dd2c255a8e3907f9dc4bbc2f47be 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1067,34 +1067,14 @@ config ARM64_ERRATUM_3117295
 
          If unsure, say Y.
 
-config ARM64_WORKAROUND_SPECULATIVE_SSBS
-       bool
-
 config ARM64_ERRATUM_3194386
-       bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing"
-       select ARM64_WORKAROUND_SPECULATIVE_SSBS
+       bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"
        default y
        help
-         This option adds the workaround for ARM Cortex-X4 erratum 3194386.
+         This option adds the workaround for the following errata:
 
-         On affected cores "MSR SSBS, #0" instructions may not affect
-         subsequent speculative instructions, which may permit unexepected
-         speculative store bypassing.
-
-         Work around this problem by placing a speculation barrier after
-         kernel changes to SSBS. The presence of the SSBS special-purpose
-         register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such
-         that userspace will use the PR_SPEC_STORE_BYPASS prctl to change
-         SSBS.
-
-         If unsure, say Y.
-
-config ARM64_ERRATUM_3312417
-       bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing"
-       select ARM64_WORKAROUND_SPECULATIVE_SSBS
-       default y
-       help
-         This option adds the workaround for ARM Neoverse-V3 erratum 3312417.
+         * ARM Cortex-X4 erratum 3194386
+         * ARM Neoverse-V3 erratum 3312417
 
          On affected cores "MSR SSBS, #0" instructions may not affect
          subsequent speculative instructions, which may permit unexepected
@@ -1108,7 +1088,6 @@ config ARM64_ERRATUM_3312417
 
          If unsure, say Y.
 
-
 config CAVIUM_ERRATUM_22375
        bool "Cavium erratum 22375, 24313"
        default y

diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 7529c02639332fdd32d97b836bc78486400c4394..a6e5b07b64fd55dd9d822e90a19ab5c6cb716998 100644 (file)
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -59,7 +59,7 @@ cpucap_is_possible(const unsigned int cap)
        case ARM64_WORKAROUND_REPEAT_TLBI:
                return IS_ENABLED(CONFIG_ARM64_WORKAROUND_REPEAT_TLBI);
        case ARM64_WORKAROUND_SPECULATIVE_SSBS:
-               return IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS);
+               return IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386);
        }
 
        return true;

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 828be635e7e1d938b7e812f6240cd9d7a070e323..5fbe14dc607f0a46434d9ff281ee5a04931f2aec 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -432,14 +432,10 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = {
 };
 #endif
 
-#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS
-static const struct midr_range erratum_spec_ssbs_list[] = {
 #ifdef CONFIG_ARM64_ERRATUM_3194386
+static const struct midr_range erratum_spec_ssbs_list[] = {
        MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
-#endif
-#ifdef CONFIG_ARM64_ERRATUM_3312417
        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
-#endif
        {}
 };
 #endif
@@ -741,7 +737,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
                MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)),
        },
 #endif
-#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS
+#ifdef CONFIG_ARM64_ERRATUM_3194386
        {
                .desc = "ARM errata 3194386, 3312417",
                .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,

diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
index baca47bd443c86e60fddd4e593dfc8faada1fc7a..da53722f95d41a3cbd650e9fa5a66bac9e827957 100644 (file)
--- a/arch/arm64/kernel/proton-pack.c
+++ b/arch/arm64/kernel/proton-pack.c
@@ -567,7 +567,7 @@ static enum mitigation_state spectre_v4_enable_hw_mitigation(void)
         * Mitigate this with an unconditional speculation barrier, as CPUs
         * could mis-speculate branches and bypass a conditional barrier.
         */
-       if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS))
+       if (IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386))
                spec_bar();
 
        return SPECTRE_MITIGATED;