drm/msm/dpu: Describe TEAR interrupt registers for DSI interfaces

All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
the PINGPONG block and into the INTF block.  Wire up the IRQ register
masks in the interrupt table for enabling, reading and clearing them.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534244/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-18-27ce1a5ab5c6@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 152d4272a087acfde4fbcee56d7e5ea78c9ae070..5e2d68ebb113e06f6eb4cc164d5bf904ccdb16c1 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -21,6 +21,10 @@
 #define MDP_INTF_INTR_EN(intf)                         (MDP_INTF_OFF(intf) + 0x1c0)
 #define MDP_INTF_INTR_STATUS(intf)                     (MDP_INTF_OFF(intf) + 0x1c4)
 #define MDP_INTF_INTR_CLEAR(intf)                      (MDP_INTF_OFF(intf) + 0x1c8)
+#define MDP_INTF_TEAR_OFF(intf)                                (0x6D700 + 0x100 * (intf))
+#define MDP_INTF_INTR_TEAR_EN(intf)                    (MDP_INTF_TEAR_OFF(intf) + 0x000)
+#define MDP_INTF_INTR_TEAR_STATUS(intf)                        (MDP_INTF_TEAR_OFF(intf) + 0x004)
+#define MDP_INTF_INTR_TEAR_CLEAR(intf)                 (MDP_INTF_TEAR_OFF(intf) + 0x008)
 #define MDP_AD4_OFF(ad4)                               (0x7C000 + 0x1000 * (ad4))
 #define MDP_AD4_INTR_EN_OFF(ad4)                       (MDP_AD4_OFF(ad4) + 0x41c)
 #define MDP_AD4_INTR_CLEAR_OFF(ad4)                    (MDP_AD4_OFF(ad4) + 0x424)
@@ -29,6 +33,10 @@
 #define MDP_INTF_REV_7xxx_INTR_EN(intf)                        (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c0)
 #define MDP_INTF_REV_7xxx_INTR_STATUS(intf)            (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c4)
 #define MDP_INTF_REV_7xxx_INTR_CLEAR(intf)             (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c8)
+#define MDP_INTF_REV_7xxx_TEAR_OFF(intf)               (0x34800 + 0x1000 * (intf))
+#define MDP_INTF_REV_7xxx_INTR_TEAR_EN(intf)           (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x000)
+#define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf)       (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x004)
+#define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf)                (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x008)
 
 /**
  * struct dpu_intr_reg - array of DPU register sets
@@ -93,6 +101,16 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
                MDP_INTF_INTR_EN(5),
                MDP_INTF_INTR_STATUS(5)
        },
+       [MDP_INTF1_TEAR_INTR] = {
+               MDP_INTF_INTR_TEAR_CLEAR(1),
+               MDP_INTF_INTR_TEAR_EN(1),
+               MDP_INTF_INTR_TEAR_STATUS(1)
+       },
+       [MDP_INTF2_TEAR_INTR] = {
+               MDP_INTF_INTR_TEAR_CLEAR(2),
+               MDP_INTF_INTR_TEAR_EN(2),
+               MDP_INTF_INTR_TEAR_STATUS(2)
+       },
        [MDP_AD4_0_INTR] = {
                MDP_AD4_INTR_CLEAR_OFF(0),
                MDP_AD4_INTR_EN_OFF(0),
@@ -113,11 +131,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
                MDP_INTF_REV_7xxx_INTR_EN(1),
                MDP_INTF_REV_7xxx_INTR_STATUS(1)
        },
+       [MDP_INTF1_7xxx_TEAR_INTR] = {
+               MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
+               MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
+               MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
+       },
        [MDP_INTF2_7xxx_INTR] = {
                MDP_INTF_REV_7xxx_INTR_CLEAR(2),
                MDP_INTF_REV_7xxx_INTR_EN(2),
                MDP_INTF_REV_7xxx_INTR_STATUS(2)
        },
+       [MDP_INTF2_7xxx_TEAR_INTR] = {
+               MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
+               MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
+               MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
+       },
        [MDP_INTF3_7xxx_INTR] = {
                MDP_INTF_REV_7xxx_INTR_CLEAR(3),
                MDP_INTF_REV_7xxx_INTR_EN(3),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index bbf475a1cb4550622306b1d3d57c5e2a1e749065..1f2dabc54c2299a7b982ff6b14ccffb55315e008 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -23,11 +23,15 @@ enum dpu_hw_intr_reg {
        MDP_INTF3_INTR,
        MDP_INTF4_INTR,
        MDP_INTF5_INTR,
+       MDP_INTF1_TEAR_INTR,
+       MDP_INTF2_TEAR_INTR,
        MDP_AD4_0_INTR,
        MDP_AD4_1_INTR,
        MDP_INTF0_7xxx_INTR,
        MDP_INTF1_7xxx_INTR,
+       MDP_INTF1_7xxx_TEAR_INTR,
        MDP_INTF2_7xxx_INTR,
+       MDP_INTF2_7xxx_TEAR_INTR,
        MDP_INTF3_7xxx_INTR,
        MDP_INTF4_7xxx_INTR,
        MDP_INTF5_7xxx_INTR,