arm64: dts: imx8mp: add eqos node and alias

Add EQOS GMAC node per Documentation/devicetree/bindings/net/imx-dwmac.txt ,
leave out the nvmem entries as that is not yet available, so the MAC has to
be passed in via DT by the bootloader.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c7523fd4eae9b533bd0960d40383502e3ecfc239..4e019dfcc01810c84e92b3d86781adaeae9edb15 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -18,6 +18,7 @@
 
        aliases {
                ethernet0 = &fec;
+               ethernet1 = &eqos;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
@@ -786,6 +787,28 @@
                                nvmem_macaddr_swap;
                                status = "disabled";
                        };
+
+                       eqos: ethernet@30bf0000 {
+                               compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
+                               reg = <0x30bf0000 0x10000>;
+                               interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "eth_wake_irq", "macirq";
+                               clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
+                                        <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
+                                        <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
+                                        <&clk IMX8MP_CLK_ENET_QOS>;
+                               clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
+                               assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
+                                                 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
+                                                 <&clk IMX8MP_CLK_ENET_QOS>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+                                                        <&clk IMX8MP_SYS_PLL2_100M>,
+                                                        <&clk IMX8MP_SYS_PLL2_125M>;
+                               assigned-clock-rates = <0>, <100000000>, <125000000>;
+                               intf_mode = <&gpr 0x4>;
+                               status = "disabled";
+                       };
                };
 
                gic: interrupt-controller@38800000 {