value type: <u32>
        Definition: LP register offset. default it is 0x34.
 
+   - clocks
+      Usage: optional, required if SNVS LP RTC requires explicit
+          enablement of clocks
+      Value type: <prop_encoded-array>
+      Definition:  a clock specifier describing the clock required for
+          enabling and disabling SNVS LP RTC.
+
+   - clock-names
+      Usage: optional, required if SNVS LP RTC requires explicit
+          enablement of clocks
+      Value type: <string>
+      Definition: clock name string should be "snvs-rtc".
+
 EXAMPLE
        sec_mon_rtc_lp@1 {
                compatible = "fsl,sec-v4.0-mon-rtc-lp";
                interrupts = <93 2>;
                regmap = <&snvs>;
                offset = <0x34>;
+               clocks = <&clks IMX7D_SNVS_CLK>;
+               clock-names = "snvs-rtc";
        };
 
 =====================================================================
                        regmap = <&sec_mon>;
                        offset = <0x34>;
                        interrupts = <93 2>;
+                       clocks = <&clks IMX7D_SNVS_CLK>;
+                       clock-names = "snvs-rtc";
                };
 
                snvs-pwrkey@020cc000 {
 
                                        offset = <0x34>;
                                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
                                                     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_SNVS_CLK>;
+                                       clock-names = "snvs-rtc";
                                };
 
                                snvs_poweroff: snvs-poweroff {