iio: adc: rockchip: correct alignment of timestamp

I assume this device is only used on architectures where a 8 byte
integer type is always 8 byte aligned.  However, I would prefer IIO
drivers to never make that assumption as the code gets copied into
new drivers which are not so tightly couple to one driver and those
can run on architectures that align these types to only 4 bytes in which
case this structure may be 4 byte to small leading to a buffer overrun.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20241215182912.481706-21-jic23@kernel.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index 240cfa391674e7deefaa9f2a51c8c825f300f577..bf434009403111a4ed25acbd4ead87a8bc65dd00 100644 (file)
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -363,7 +363,7 @@ static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
         */
        struct {
                u16 values[SARADC_MAX_CHANNELS];
-               int64_t timestamp;
+               aligned_s64 timestamp;
        } data;
        int ret;
        int i, j = 0;