ARM: dts: stm32: Add USB HS support for STM32F746 MCU

This patch adds the USB pins and nodes for USB HS core on STM32F746 SoC.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index faaeca803943fbb44e06fbe262a31d92d5707d8a..91556ebc5594b3e8fe1e32e39900fe9275ee06ea 100644 (file)
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -661,6 +661,46 @@
                                        slew-rate = <0>;
                                };
                        };
+
+                       usbotg_hs_pins_a: usbotg-hs@0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
+                                                <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
+                                                <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+                                                <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+                                                <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+                                                <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+                                                <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+                                                <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+                                                <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+                                                <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+                                                <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+                                                <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <2>;
+                               };
+                       };
+
+                       usbotg_hs_pins_b: usbotg-hs@1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
+                                                <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
+                                                <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+                                                <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+                                                <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+                                                <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+                                                <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+                                                <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+                                                <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+                                                <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+                                                <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+                                                <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <2>;
+                               };
+                       };
                };
 
                crc: crc@40023000 {
@@ -713,6 +753,15 @@
                        st,mem2mem;
                        status = "disabled";
                };
+
+               usbotg_hs: usb@40040000 {
+                       compatible = "st,stm32f7-hsotg";
+                       reg = <0x40040000 0x40000>;
+                       interrupts = <77>;
+                       clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
+                       clock-names = "otg";
+                       status = "disabled";
+               };
        };
 };