arm64: dts: ls1043a: Add cache nodes for cacheinfo support

Adds the cache nodes and next-level-cache property for the
cacheinfo to work.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index c451b814ac74a1e46a537da6822c9fef1c384d12..19572d85c80db7d27a8ff5f7e98a4fb99890eee3 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -65,6 +65,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0>;
                        clocks = <&clockgen 1 0>;
+                       next-level-cache = <&l2>;
                };
 
                cpu1: cpu@1 {
@@ -72,6 +73,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x1>;
                        clocks = <&clockgen 1 0>;
+                       next-level-cache = <&l2>;
                };
 
                cpu2: cpu@2 {
@@ -79,6 +81,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x2>;
                        clocks = <&clockgen 1 0>;
+                       next-level-cache = <&l2>;
                };
 
                cpu3: cpu@3 {
@@ -86,6 +89,11 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x3>;
                        clocks = <&clockgen 1 0>;
+                       next-level-cache = <&l2>;
+               };
+
+               l2: l2-cache {
+                       compatible = "cache";
                };
        };