static inline bool thread_sm_enabled(struct thread_struct *thread)
{
- return system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK);
+ return system_supports_sme() && (thread->svcr & SVCR_SM_MASK);
}
static inline bool thread_za_enabled(struct thread_struct *thread)
{
- return system_supports_sme() && (thread->svcr & SVCR_EL0_ZA_MASK);
+ return system_supports_sme() && (thread->svcr & SVCR_ZA_MASK);
}
/* Maximum VL that SVE/SME VL-agnostic software can transparently support */
static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
{
- if (system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK))
+ if (system_supports_sme() && (thread->svcr & SVCR_SM_MASK))
return thread_get_sme_vl(thread);
else
return thread_get_sve_vl(thread);
#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
-#define SYS_SVCR_EL0 sys_reg(3, 3, 4, 2, 2)
-#define SVCR_EL0_ZA_MASK 2
-#define SVCR_EL0_SM_MASK 1
+#define SYS_SVCR sys_reg(3, 3, 4, 2, 2)
+#define SVCR_ZA_MASK 2
+#define SVCR_SM_MASK 1
#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
if (test_thread_flag(TIF_SME))
sme_set_vq(sve_vq_from_vl(sme_vl) - 1);
- write_sysreg_s(current->thread.svcr, SYS_SVCR_EL0);
+ write_sysreg_s(current->thread.svcr, SYS_SVCR);
if (thread_za_enabled(¤t->thread))
za_load_state(current->thread.za_state);
if (system_supports_sme()) {
u64 *svcr = last->svcr;
- *svcr = read_sysreg_s(SYS_SVCR_EL0);
+ *svcr = read_sysreg_s(SYS_SVCR);
- *svcr = read_sysreg_s(SYS_SVCR_EL0);
+ *svcr = read_sysreg_s(SYS_SVCR);
- if (*svcr & SYS_SVCR_EL0_ZA_MASK)
+ if (*svcr & SVCR_ZA_MASK)
za_save_state(last->za_state);
/* If we are in streaming mode override regular SVE. */
- if (*svcr & SYS_SVCR_EL0_SM_MASK) {
+ if (*svcr & SVCR_SM_MASK) {
save_sve_regs = true;
save_ffr = system_supports_fa64();
vl = last->sme_vl;
sve_to_fpsimd(task);
if (system_supports_sme() && type == ARM64_VEC_SME) {
- task->thread.svcr &= ~(SYS_SVCR_EL0_SM_MASK |
- SYS_SVCR_EL0_ZA_MASK);
+ task->thread.svcr &= ~(SVCR_SM_MASK |
+ SVCR_ZA_MASK);
clear_thread_flag(TIF_SME);
}
__this_cpu_write(efi_sve_state_used, true);
if (system_supports_sme()) {
- svcr = read_sysreg_s(SYS_SVCR_EL0);
+ svcr = read_sysreg_s(SYS_SVCR);
if (!system_supports_fa64())
- ffr = svcr & SVCR_EL0_SM_MASK;
+ ffr = svcr & SVCR_SM_MASK;
__this_cpu_write(efi_sm_state, ffr);
}
ffr);
if (system_supports_sme())
- sysreg_clear_set_s(SYS_SVCR_EL0,
- SVCR_EL0_SM_MASK, 0);
+ sysreg_clear_set_s(SYS_SVCR,
+ SVCR_SM_MASK, 0);
} else {
fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
*/
if (system_supports_sme()) {
if (__this_cpu_read(efi_sm_state)) {
- sysreg_clear_set_s(SYS_SVCR_EL0,
+ sysreg_clear_set_s(SYS_SVCR,
0,
- SVCR_EL0_SM_MASK);
+ SVCR_SM_MASK);
if (!system_supports_fa64())
ffr = efi_sm_state;
}
switch (type) {
case ARM64_VEC_SVE:
- target->thread.svcr &= ~SYS_SVCR_EL0_SM_MASK;
+ target->thread.svcr &= ~SVCR_SM_MASK;
break;
case ARM64_VEC_SME:
- target->thread.svcr |= SYS_SVCR_EL0_SM_MASK;
+ target->thread.svcr |= SVCR_SM_MASK;
break;
default:
WARN_ON_ONCE(1);
/* If there is no data then disable ZA */
if (!count) {
- target->thread.svcr &= ~SYS_SVCR_EL0_ZA_MASK;
+ target->thread.svcr &= ~SVCR_ZA_MASK;
goto out;
}
/* Mark ZA as active and let userspace use it */
set_tsk_thread_flag(target, TIF_SME);
- target->thread.svcr |= SYS_SVCR_EL0_ZA_MASK;
+ target->thread.svcr |= SVCR_ZA_MASK;
out:
fpsimd_flush_task_state(target);
if (sve.head.size <= sizeof(*user->sve)) {
clear_thread_flag(TIF_SVE);
- current->thread.svcr &= ~SYS_SVCR_EL0_SM_MASK;
+ current->thread.svcr &= ~SVCR_SM_MASK;
goto fpsimd_only;
}
return -EFAULT;
if (sve.flags & SVE_SIG_FLAG_SM)
- current->thread.svcr |= SYS_SVCR_EL0_SM_MASK;
+ current->thread.svcr |= SVCR_SM_MASK;
else
set_thread_flag(TIF_SVE);
return -EINVAL;
if (za.head.size <= sizeof(*user->za)) {
- current->thread.svcr &= ~SYS_SVCR_EL0_ZA_MASK;
+ current->thread.svcr &= ~SVCR_ZA_MASK;
return 0;
}
sme_alloc(current);
if (!current->thread.za_state) {
- current->thread.svcr &= ~SYS_SVCR_EL0_ZA_MASK;
+ current->thread.svcr &= ~SVCR_ZA_MASK;
clear_thread_flag(TIF_SME);
return -ENOMEM;
}
return -EFAULT;
set_thread_flag(TIF_SME);
- current->thread.svcr |= SYS_SVCR_EL0_ZA_MASK;
+ current->thread.svcr |= SVCR_ZA_MASK;
return 0;
}
/* Signal handlers are invoked with ZA and streaming mode disabled */
if (system_supports_sme()) {
- current->thread.svcr &= ~(SYS_SVCR_EL0_ZA_MASK |
- SYS_SVCR_EL0_SM_MASK);
+ current->thread.svcr &= ~(SVCR_ZA_MASK |
+ SVCR_SM_MASK);
sme_smstop();
}
* need updating.
*/
if (system_supports_sme() && test_thread_flag(TIF_SME)) {
- u64 svcr = read_sysreg_s(SYS_SVCR_EL0);
+ u64 svcr = read_sysreg_s(SYS_SVCR);
- if (svcr & SYS_SVCR_EL0_SM_MASK)
+ if (svcr & SVCR_SM_MASK)
sme_smstop_sm();
}
if (read_sysreg(cpacr_el1) & CPACR_EL1_SMEN_EL0EN)
vcpu->arch.flags |= KVM_ARM64_HOST_SME_ENABLED;
- if (read_sysreg_s(SYS_SVCR_EL0) &
- (SYS_SVCR_EL0_SM_MASK | SYS_SVCR_EL0_ZA_MASK)) {
+ if (read_sysreg_s(SYS_SVCR) &
+ (SVCR_SM_MASK | SVCR_ZA_MASK)) {
vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
fpsimd_save_and_flush_cpu_state();
}
{ SYS_DESC(SYS_SMIDR_EL1), undef_access },
{ SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
{ SYS_DESC(SYS_CTR_EL0), access_ctr },
- { SYS_DESC(SYS_SVCR_EL0), undef_access },
+ { SYS_DESC(SYS_SVCR), undef_access },
{ PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr,
.reset = reset_pmcr, .reg = PMCR_EL0 },