Modifications for 1.0.5:
======================================================================
+* Major modification for GTH board;
+ added CONFIG_RESET_TO_RETRY configuration option
+ Patch by Thomas Lange, 09 Aug 2001
+
* Add I2C and SPI microcode relocation patches (MPC8xx)
Based on a patch by Joakim Tjernlund, 23 Aug 2001
CONFIG_AUTOBOOT_DELAY_STR
CONFIG_AUTOBOOT_STOP_STR
CONFIG_ZERO_BOOTDELAY_CHECK
+ CONFIG_RESET_TO_RETRY
- Autoboot Command:
CONFIG_BOOTCOMMAND
#
-# (C) Copyright 2000
+# (C) Copyright 2000, 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+OBJS = $(BOARD).o flash.o ee_access.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
--- /dev/null
+Written by Thomas.Lange@corelatus.com 010805
+
+To make a system for gth that actually works ;-)
+the variable TBASE needs to be set to 0,1 or 2
+depending on location where image is supposed to
+be started from.
+E.g. make TBASE=1
+
+0: Start from RAM, base 0
+
+1: Start from flash_base + 0x10070
+
+2: Start from flash_base + 0x30070
+
+When using 1 or 2, the image is supposed to be launched
+from miniboot that boots the first ppcboot image found in
+flash.
+For miniboot code, description, see www.opensource.se
+
+
#
-# (C) Copyright 2000
+# (C) Copyright 2000, 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
#
-ifeq ($(CONFIG_START_IN_RAM),1)
+ifeq ($(TBASE),0)
TEXT_BASE = 0
else
-TEXT_BASE = 0x080000000
+ifeq ($(TBASE),1)
+TEXT_BASE = 0x80010070
+else
+ifeq ($(TBASE),2)
+TEXT_BASE = 0x80030070
+else
+## Only to make ordinary make work
+TEXT_BASE = 0x90000000
+endif
endif
+endif
+
OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
--- /dev/null
+/* Module for handling DALLAS DS2438, smart battery monitor
+ Chip can store up to 40 bytes of user data in EEPROM,
+ perform temp, voltage and current measurements.
+ Chip also contains a unique serial number.
+
+ Always read/write LSb first
+
+ For documentaion, see data sheet for DS2438, 2438.pdf
+
+ By Thomas.Lange@corelatus.com 001025 */
+
+#include <ppcboot.h>
+#include <config.h>
+#include "mpc8xx.h"
+
+#include <../board/gth/ee_dev.h>
+
+/* We dont have kernel functions */
+#define printk printf
+#define KERN_DEBUG
+#define KERN_ERR
+#define EIO 1
+
+static int Debug = 0;
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/*
+ * lookup table ripped from DS app note 17, understanding and using
+ * cyclic redundancy checks...
+ */
+
+static u8 crc_lookup[256] = {
+ 0, 94, 188, 226, 97, 63, 221, 131,
+ 194, 156, 126, 32, 163, 253, 31, 65,
+ 157, 195, 33, 127, 252, 162, 64, 30,
+ 95, 1, 227, 189, 62, 96, 130, 220,
+ 35, 125, 159, 193, 66, 28, 254, 160,
+ 225, 191, 93, 3, 128, 222, 60, 98,
+ 190, 224, 2, 92, 223, 129, 99, 61,
+ 124, 34, 192, 158, 29, 67, 161, 255,
+ 70, 24, 250, 164, 39, 121, 155, 197,
+ 132, 218, 56, 102, 229, 187, 89, 7,
+ 219, 133, 103, 57, 186, 228, 6, 88,
+ 25, 71, 165, 251, 120, 38, 196, 154,
+ 101, 59, 217, 135, 4, 90, 184, 230,
+ 167, 249, 27, 69, 198, 152, 122, 36,
+ 248, 166, 68, 26, 153, 199, 37, 123,
+ 58, 100, 134, 216, 91, 5, 231, 185,
+ 140, 210, 48, 110, 237, 179, 81, 15,
+ 78, 16, 242, 172, 47, 113, 147, 205,
+ 17, 79, 173, 243, 112, 46, 204, 146,
+ 211, 141, 111, 49, 178, 236, 14, 80,
+ 175, 241, 19, 77, 206, 144, 114, 44,
+ 109, 51, 209, 143, 12, 82, 176, 238,
+ 50, 108, 142, 208, 83, 13, 239, 177,
+ 240, 174, 76, 18, 145, 207, 45, 115,
+ 202, 148, 118, 40, 171, 245, 23, 73,
+ 8, 86, 180, 234, 105, 55, 213, 139,
+ 87, 9, 235, 181, 54, 104, 138, 212,
+ 149, 203, 41, 119, 244, 170, 72, 22,
+ 233, 183, 85, 11, 136, 214, 52, 106,
+ 43, 117, 151, 201, 74, 20, 246, 168,
+ 116, 42, 200, 150, 21, 75, 169, 247,
+ 182, 232, 10, 84, 215, 137, 107, 53
+};
+
+static u8 make_new_crc( u8 Old_crc, u8 New_value ){
+ /* Compute a new checksum with new byte, using previous checksum as input
+ See DS app note 17, understanding and using cyclic redundancy checks...
+ Also see DS2438, page 11 */
+ return( crc_lookup[Old_crc ^ New_value ]);
+}
+
+int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
+ /* Check if the checksum for this buffer is correct */
+ u8 Curr_crc=0;
+ int i;
+ u8 *Curr_byte = Buffer;
+
+ for(i=0;i<Len;i++){
+ Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
+ Curr_byte++;
+ }
+ E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
+
+ if(Curr_crc == Crc){
+ /* Good */
+ return(TRUE);
+ }
+ printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n",
+ Curr_crc, Crc);
+ return(FALSE);
+}
+
+static void
+set_idle(void){
+ /* Send idle and keep start time
+ Continous 1 is idle */
+ WRITE_PORT(1);
+}
+
+static int
+do_reset(void){
+ /* Release reset and verify that chip responds with presence pulse */
+ int Retries;
+ while(Retries<5){
+ udelay(RESET_LOW_TIME);
+
+ /* Send reset */
+ WRITE_PORT(0);
+ udelay(RESET_LOW_TIME);
+
+ /* Release reset */
+ WRITE_PORT(1);
+
+ /* Wait for EEPROM to drive output */
+ udelay(PRESENCE_TIMEOUT);
+ if(!READ_PORT){
+ /* Ok, EEPROM is driving a 0 */
+ E_DEBUG("Presence detected\n");
+ if(Retries){
+ E_DEBUG("Retries %d\n",Retries);
+ }
+ /* Make sure chip releases pin */
+ udelay(PRESENCE_LOW_TIME);
+ return 0;
+ }
+ Retries++;
+ }
+
+ printk(KERN_ERR"EEPROM did not respond when releasing reset\n");
+
+ /* Make sure chip releases pin */
+ udelay(PRESENCE_LOW_TIME);
+
+ /* Set to idle again */
+ set_idle();
+
+ return(-EIO);
+}
+
+static u8
+read_byte(void){
+ /* Read a single byte from EEPROM
+ Read LSb first */
+ int i;
+ int Value;
+ u8 Result=0;
+#ifndef CFG_IMMR
+ u32 Flags;
+#endif
+
+ E_DEBUG("Reading byte\n");
+
+ for(i=0;i<8;i++){
+ /* Small delay between pulses */
+ udelay(1);
+
+#ifndef CFG_IMMR
+ /* Disable irq */
+ save_flags(Flags);
+ cli();
+#endif
+
+ /* Pull down pin short time to start read
+ See page 26 in data sheet */
+
+ WRITE_PORT(0);
+ udelay(READ_LOW);
+ WRITE_PORT(1);
+
+ /* Wait for chip to drive pin */
+ udelay(READ_TIMEOUT);
+
+ Value = READ_PORT;
+ if(Value)
+ Value=1;
+
+#ifndef CFG_IMMR
+ /* Enable irq */
+ restore_flags(Flags);
+#endif
+
+ /* Wait for chip to release pin */
+ udelay(TOTAL_READ_LOW-READ_TIMEOUT);
+
+ /* LSb first */
+ Result|=Value<<i;
+ }
+
+ E_DEBUG("Read byte 0x%x\n",Result);
+
+ return(Result);
+}
+
+static void
+write_byte(u8 Byte){
+ /* Write a single byte to EEPROM
+ Write LSb first */
+ int i;
+ int Value;
+#ifndef CFG_IMMR
+ u32 Flags;
+#endif
+
+ E_DEBUG("Writing byte 0x%x\n",Byte);
+
+ for(i=0;i<8;i++){
+ /* Small delay between pulses */
+ udelay(1);
+ Value = Byte&1;
+
+#ifndef CFG_IMMR
+ /* Disable irq */
+ save_flags(Flags);
+ cli();
+#endif
+
+ /* Pull down pin short time for a 1, long time for a 0
+ See page 26 in data sheet */
+
+ WRITE_PORT(0);
+ if(Value){
+ /* Write a 1 */
+ udelay(WRITE_1_LOW);
+ }
+ else{
+ /* Write a 0 */
+ udelay(WRITE_0_LOW);
+ }
+
+ WRITE_PORT(1);
+
+#ifndef CFG_IMMR
+ /* Enable irq */
+ restore_flags(Flags);
+#endif
+
+ if(Value)
+ /* Wait for chip to read the 1 */
+ udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
+ Byte>>=1;
+ }
+}
+
+int ee_do_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
+ /* Execute this command string, including
+ giving reset and setting to idle after command
+ if Rx_len is set, we read out data from EEPROM */
+ int i;
+
+ E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
+
+ if(do_reset()){
+ /* Failed! */
+ return(-EIO);
+ }
+
+ if(Send_skip)
+ /* Always send SKIP_ROM first to tell chip we are sending a command,
+ except when we read out rom data for chip */
+ write_byte(SKIP_ROM);
+
+ /* Always have Tx data */
+ for(i=0;i<Tx_len;i++){
+ write_byte(Tx[i]);
+ }
+
+ if(Rx_len){
+ for(i=0;i<Rx_len;i++){
+ Rx[i]=read_byte();
+ }
+ }
+
+ set_idle();
+
+ E_DEBUG("Command done\n");
+
+ return(0);
+}
+
+int ee_init_data(void){
+ int i;
+ u8 Tx[10];
+ int tmp;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+ while(0){
+ tmp = 1-tmp;
+ if(tmp)
+ immap->im_ioport.iop_padat &= ~PA_FRONT_LED;
+ else
+ immap->im_ioport.iop_padat |= PA_FRONT_LED;
+ udelay(1);
+ }
+
+ /* Set port to open drain to be able to read data from
+ port without setting it to input */
+ PORT_B_PAR &= ~PB_EEPROM;
+ PORT_B_ODR |= PB_EEPROM;
+ SET_PORT_B_OUTPUT(PB_EEPROM);
+
+ /* Set idle mode */
+ set_idle();
+
+ /* Copy all User EEPROM data to scratchpad */
+ for(i=0;i<USER_PAGES;i++){
+ Tx[0]=RECALL_MEMORY;
+ Tx[1]=EE_USER_PAGE_0+i;
+ if(ee_do_command(Tx,2,NULL,0,TRUE)) return(-EIO);
+ }
+
+ /* Make sure chip doesnt store measurements in NVRAM */
+ Tx[0]=WRITE_SCRATCHPAD;
+ Tx[1]=0; /* Page */
+ Tx[2]=9;
+ if(ee_do_command(Tx,3,NULL,0,TRUE)) return(-EIO);
+
+ Tx[0]=COPY_SCRATCHPAD;
+ if(ee_do_command(Tx,2,NULL,0,TRUE)) return(-EIO);
+
+ /* FIXME check status bit instead
+ Could take 10 ms to store in EEPROM */
+ for(i=0;i<10;i++){
+ udelay(1000);
+ }
+
+ return(0);
+}
--- /dev/null
+/* By Thomas.Lange@Corelatus.com 001025
+
+ Definitions for EEPROM/VOLT METER DS2438 */
+
+#ifndef INCeeaccessh
+#define INCeeaccessh
+
+int ee_do_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
+int ee_init_data(void);
+int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#endif /* INCeeaccessh */
--- /dev/null
+/* By Thomas.Lange@Corelatus.com 001025
+ $Revision: 1.6 $
+
+ Definitions for EEPROM/VOLT METER DS2438
+ Copyright (C) 2000-2001 Corelatus AB */
+
+#ifndef INCeedevh
+#define INCeedevh
+
+#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
+
+#define PORT_B_PAR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbpar
+#define PORT_B_ODR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbodr
+#define PORT_B_DIR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdir
+#define PORT_B_DAT ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat
+
+#define SET_PORT_B_INPUT(Mask) PORT_B_DIR &= ~(Mask)
+#define SET_PORT_B_OUTPUT(Mask) PORT_B_DIR |= Mask
+
+#define WRITE_PORT_B(Mask,Value) { \
+ if (Value) PORT_B_DAT |= Mask; \
+ else PORT_B_DAT &= ~(Mask); \
+ }
+#define WRITE_PORT(Value) WRITE_PORT_B(PB_EEPROM,Value)
+
+#define READ_PORT (PORT_B_DAT&PB_EEPROM)
+
+/* 64 bytes chip */
+#define EE_CHIP_SIZE 64
+
+/* We use this resistor for measuring the current drain on 3.3V */
+#define CURRENT_RESISTOR 0.022
+
+/* microsecs
+ Pull line down at least this long for reset pulse */
+#define RESET_LOW_TIME 490
+
+/* Read presence pulse after we release reset pulse */
+#define PRESENCE_TIMEOUT 100
+#define PRESENCE_LOW_TIME 200
+
+#define WRITE_0_LOW 80
+#define WRITE_1_LOW 2
+#define TOTAL_WRITE_LOW 80
+
+#define READ_LOW 2
+#define READ_TIMEOUT 10
+#define TOTAL_READ_LOW 80
+
+/*** Rom function commands ***/
+#define READ_ROM 0x33
+#define MATCH_ROM 0x55
+#define SKIP_ROM 0xCC
+#define SEARCH_ROM 0xF0
+
+
+/*** Memory_command_function ***/
+#define WRITE_SCRATCHPAD 0x4E
+#define READ_SCRATCHPAD 0xBE
+#define COPY_SCRATCHPAD 0x48
+#define RECALL_MEMORY 0xB8
+#define CONVERT_TEMP 0x44
+#define CONVERT_VOLTAGE 0xB4
+
+/* Chip is divided in 8 pages, 8 bytes each */
+
+#define EE_PAGE_SIZE 8
+
+/* All chip data we want are in page 0 */
+
+/* Bytes in page 0 */
+#define EE_P0_STATUS 0
+#define EE_P0_TEMP_LSB 1
+#define EE_P0_TEMP_MSB 2
+#define EE_P0_VOLT_LSB 3
+#define EE_P0_VOLT_MSB 4
+#define EE_P0_CURRENT_LSB 5
+#define EE_P0_CURRENT_MSB 6
+
+
+/* 40 byte user data is located at page 3-7 */
+#define EE_USER_PAGE_0 3
+#define USER_PAGES 5
+
+#endif /* INCeedevh */
unsigned long size_b0, size_b1;
int i;
- //printf("faking");
+ /*printf("faking");*/
return(0x4fffff);
if (flash_info[0].flash_id == FLASH_UNKNOWN)
{
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",size_b0, size_b0<<20);
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
}
#if 0
if (FLASH_BASE1_PRELIM != 0x0) {
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",size_b1, size_b1<<20,size_b0, size_b0<<20);
-
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
+ size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+ if (size_b1 > size_b0) {
+ printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+ size_b1, size_b1<<20,size_b0, size_b0<<20);
+
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[0].sector_count = -1;
+ flash_info[1].sector_count = -1;
+ flash_info[0].size = 0;
+ flash_info[1].size = 0;
+ return (0);
+ }
} else {
#endif
size_b1 = 0;
-// }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CFG_OR0_PRELIM;
- memctl->memc_br0 = CFG_BR0_PRELIM;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
-
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR0_PRELIM;
+ memctl->memc_br0 = CFG_BR0_PRELIM;
+
+ /* Re-do sizing to get full correct info */
+ size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
if (size_b1)
{
- //memctl->memc_or1 = CFG_OR1_PRELIM;
- //memctl->memc_br1 = CFG_BR1_PRELIM;
+ /* memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM; */
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
}
else
{
-// memctl->memc_or1 = CFG_OR1_PRELIM;
-// FIXME memctl->memc_br1 = CFG_BR1_PRELIM;
+/* memctl->memc_or1 = CFG_OR1_PRELIM;
+ FIXME memctl->memc_br1 = CFG_BR1_PRELIM; */
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
#include <ppcboot.h>
#include <config.h>
#include "mpc8xx.h"
+#include "ee_access.h"
+#include "ee_dev.h"
#ifdef CONFIG_BDM
#undef printf
int Id=0;
int Rev=0;
u32 Pbdat;
- // Turn on leds and setup for reading rev and id
+ /* Turn on leds and setup for reading rev and id */
#define PB_OUTS (PB_BLUE_LED|PB_ID_GND)
#define PB_INS (PB_ID_0|PB_ID_1|PB_ID_2|PB_ID_3|PB_REV_1|PB_REV_0)
immap->im_cpm.cp_pbodr |= PB_OUTS;
immap->im_cpm.cp_pbdat &= ~PB_OUTS;
- // Turn on front led to show that we are alive
+ /* Hold 100 Mbit in reset until fpga is loaded */
+ immap->im_ioport.iop_pcpar &= ~PC_ENET100_RESET;
+ immap->im_ioport.iop_pcdir |= PC_ENET100_RESET;
+ immap->im_ioport.iop_pcso &= ~PC_ENET100_RESET;
+ immap->im_ioport.iop_pcdat &= ~PC_ENET100_RESET;
+
+ /* Turn on front led to show that we are alive */
immap->im_ioport.iop_papar &= ~PA_FRONT_LED;
immap->im_ioport.iop_padir |= PA_FRONT_LED;
immap->im_ioport.iop_paodr |= PA_FRONT_LED;
if(Pbdat&PB_REV_0) Rev +=1;
if(Pbdat&PB_REV_1) Rev +=2;
- // Turn ID off since we dont need it anymore
+ /* Turn ID off since we dont need it anymore */
immap->im_cpm.cp_pbdat |= PB_ID_GND;
printf("GTH board, rev %d, id=0x%01x\n",Rev,Id);
#define _NOT_USED_ 0xffffffff
const uint sdram_table[] = {
- // Single read, offset 0
+ /* Single read, offset 0 */
0x0f3dfc04, 0x0eefbc04, 0x01bf7c04, 0x0feafc00,
0x1fb5fc45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- // Burst read, Offset 0x8, 4 reads,
+ /* Burst read, Offset 0x8, 4 reads */
0x0f3dfc04, 0x0eefbc04, 0x00bf7c04, 0x00ffec00,
0x00fffc00, 0x01eafc00, 0x1fb5fc00, 0xfffffc45,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- // Not used part of burst read is used for MRS, Offset 0x14
+ /* Not used part of burst read is used for MRS, Offset 0x14 */
0xefeabc34, 0x1fb57c34, 0xfffffc05, _NOT_USED_,
- // _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */
- // Single write, Offset 0x18
+ /* Single write, Offset 0x18 */
0x0f3dfc04, 0x0eebbc00, 0x01a27c04, 0x1fb5fc45,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- // Burst write, Offset 0x20. 4 writes
+ /* Burst write, Offset 0x20. 4 writes */
0x0f3dfc04, 0x0eebbc00, 0x00b77c00, 0x00fffc00,
0x00fffc00, 0x01eafc04, 0x1fb5fc45, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- // Not used part of burst write is used for precharge, Offset 0x2C
+ /* Not used part of burst write is used for precharge, Offset 0x2C */
0x0ff5fc04, 0xfffffc05, _NOT_USED_, _NOT_USED_,
- // _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */
- // Period timer service. Offset 0x30. Refresh. Wait at least 70 ns after refresh command
+ /* Period timer service. Offset 0x30. Refresh. Wait at least 70 ns after refresh command */
0x1ffd7c04, 0xfffffc04, 0xfffffc04, 0xfffffc05,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- // Exception, Offset 0x3C
+ /* Exception, Offset 0x3C */
0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_ };
const uint fpga_table[] = {
- // Single read, offset 0
+ /* Single read, offset 0 */
0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
- // Burst read, Offset 0x8
+ /* Burst read, Offset 0x8 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- // Single write, Offset 0x18
+ /* Single write, Offset 0x18 */
0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
- // Burst write, Offset 0x20.
+ /* Burst write, Offset 0x20. */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- // Period timer service. Offset 0x30.
+ /* Period timer service. Offset 0x30. */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- // Exception, Offset 0x3C
+ /* Exception, Offset 0x3C */
0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_ };
int _initsdram(uint base, uint noMbytes){
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *mc = &immap->im_memctl;
- mc->memc_mptpr = MPTPR_PTP_DIV16; // (16-17)
-
- ///// Setup SDRAM in UPMA /////
-
- // GPL_0 is connected instead of A19 to SDRAM.
- // According to table 16-17, AMx should be 001, i.e. type 1
- // and GPL_0 should hold address A10 when multiplexing
+ mc->memc_mptpr = MPTPR_PTP_DIV16; /* (16-17) */
+ /* SDRAM in UPMA
+
+ GPL_0 is connected instead of A19 to SDRAM.
+ According to table 16-17, AMx should be 001, i.e. type 1
+ and GPL_0 should hold address A10 when multiplexing */
+
mc->memc_mamr = (0x2E<<MAMR_PTA_SHIFT)|MAMR_PTAE|MAMR_AMA_TYPE_1|MAMR_G0CLA_A10|
- MAMR_RLFA_1X|MAMR_WLFA_1X|MAMR_TLFA_1X; // (16-13)
+ MAMR_RLFA_1X|MAMR_WLFA_1X|MAMR_TLFA_1X; /* (16-13) */
upmconfig(UPMA, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
- // Perform init of sdram ( Datasheet Page 9 )
- // Precharge
- mc->memc_mcr = 0x8000212C; // run upm a at 0x2C (16-15)
+ /* Perform init of sdram ( Datasheet Page 9 )
+ Precharge */
+ mc->memc_mcr = 0x8000212C; /* run upm a at 0x2C (16-15) */
- // Run 2 refresh cycles
- mc->memc_mcr = 0x80002130; // run upm a at 0x30 (16-15)
- mc->memc_mcr = 0x80002130; // run upm a at 0x30 (16-15)
+ /* Run 2 refresh cycles */
+ mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */
+ mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */
- // Set Mode register
- mc->memc_mar = 0x00000088; // set mode register (address) to 0x022 (16-17) Lower 2 bits are not connected to chip
- mc->memc_mcr = 0x80002114; // run upm a at 0x14 (16-15)
+ /* Set Mode register */
+ mc->memc_mar = 0x00000088; /* set mode register (address) to 0x022 (16-17) */
+ /* Lower 2 bits are not connected to chip */
+ mc->memc_mcr = 0x80002114; /* run upm a at 0x14 (16-15) */
- //FIXME when not 32MB
- // CS1, base 0x0000000 - 32 Mbyte, use UPM A
+ /* FIXME when not 32MB */
+ /* CS1, base 0x0000000 - 32 Mbyte, use UPM A */
mc->memc_or1 = 0xfe000000|OR_CSNT_SAM;
- mc->memc_br1 = BR_MS_UPMA|BR_V; // SDRAM base always 0
+ mc->memc_br1 = BR_MS_UPMA|BR_V; /* SDRAM base always 0 */
- ///// Setup FPGA in UPMB /////
+ /* Setup FPGA in UPMB */
upmconfig(UPMB, (uint *)fpga_table,sizeof(fpga_table)/sizeof(uint));
- // Enable UPWAITB
- mc->memc_mbmr = MAMR_GPL_B4DIS; // (16-13)
+ /* Enable UPWAITB */
+ mc->memc_mbmr = MAMR_GPL_B4DIS; /* (16-13) */
- // CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit
+ /* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */
mc->memc_or2 = 0xffc00000| OR_BI;
mc->memc_br2 = FPGA_2_BASE|BR_MS_UPMB|BR_V;
- // CS3, base FPGA_3_BASE - 4 MByte, use UPM B 16 bit
+ /* CS3, base FPGA_3_BASE - 4 MByte, use UPM B 16 bit */
mc->memc_or3 = 0xffc00000|OR_BI;
mc->memc_br3 = FPGA_3_BASE|BR_MS_UPMB|BR_V|BR_PS_16;
*noMbytes = 32;
#ifdef CONFIG_START_IN_RAM
- // SDRAM is already setup. Dont touch it
+ /* SDRAM is already setup. Dont touch it */
return 0;
#else
u32 *i;
u32 j;
u32 k;
- // GTH only have SDRAM
+ /* GTH only have SDRAM */
uint sdramsz;
if (!initsdram(0x00000000, &sdramsz)) {
#define U32_S ((sdramsz<<18)-1)
#if 1
- // Do a simple memory test
+ /* Do a simple memory test */
for(i=(u32*)0,j=0;(u32)i<U32_S;i+=2,j+=2){
*i = j+(j<<17);
*(i+1) = ~(j+(j<<18));
}
#endif
- // Clear memory
+ /* Clear memory */
for(i=(u32*)0;(u32)i<U32_S;i++){
*i = 0;
}
-#endif // !start in ram
+#endif /* !start in ram */
return (sdramsz << 20);
}
+
+#define BOOTDATA_OFFSET 0xF8000
+#define MAX_ATTEMPTS 5
+
+#define FAILSAFE_BOOT 1
+#define SYSTEM_BOOT 2
+
+#define WRITE_FLASH16(a, d) \
+do \
+{ \
+ *((volatile u16 *) (a)) = (d);\
+ } while(0)
+
+static void write_bootdata( volatile u16* addr, u8 System, u8 Count ){
+ u16 data;
+ volatile u16 *flash = (u16*)(CFG_FLASH_BASE);
+
+ if((System!=FAILSAFE_BOOT)&(System!=SYSTEM_BOOT)){
+ printf("Invalid system data %u, setting failsafe\n",System);
+ System=FAILSAFE_BOOT;
+ }
+
+ if((Count<1)|(Count>MAX_ATTEMPTS)){
+ printf("Invalid boot count %u, setting 1\n",Count);
+ Count=1;
+ }
+
+ if(System==FAILSAFE_BOOT){
+ printf("Setting failsafe boot in flash\n");
+ }
+ else{
+ printf("Setting system boot in flash\n");
+ }
+ printf("Boot attempt %d\n",Count);
+
+ data = (System<<8)|Count;
+ /* AMD 16 bit */
+ WRITE_FLASH16(&flash[0x555], 0xAAAA);
+ WRITE_FLASH16(&flash[0x2AA], 0x5555);
+ WRITE_FLASH16(&flash[0x555], 0xA0A0);
+
+ WRITE_FLASH16(addr, data);
+}
+
+static void check_boot_tries(void){
+ /* Count the number of boot attemps
+ switch system if too many */
+
+ int i;
+ volatile u16 *addr;
+ volatile u16 data;
+ int failsafe = 1;
+ u8 system;
+ u8 count;
+
+ addr = (u16*)(CFG_FLASH_BASE+BOOTDATA_OFFSET);
+
+ if(*addr==0xFFFF){
+ printf("*** No bootdata exists. ***\n");
+ write_bootdata( addr, FAILSAFE_BOOT, 1 );
+ }
+ else{
+ /* Search for latest written bootdata */
+ i=0;
+ while((*(addr+1)!=0xFFFF)&(i<8000)){
+ addr++;
+ i++;
+ }
+ if(i>=8000){
+ // Whoa, dont write any more
+ printf("*** No bootdata found. Not updating flash***\n");
+ }
+ else{
+ /* See how many times we have tried to boot real system */
+ data = *addr;
+ system=data>>8;
+ count=data&0xFF;
+ if((system!=SYSTEM_BOOT)&(system!=FAILSAFE_BOOT)){
+ printf("*** Wrong system %d\n",system);
+ system=FAILSAFE_BOOT;
+ count=1;
+ }
+ else{
+ switch(count){
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ // Try same system again if needed
+ count++;
+ break;
+
+ case 5:
+ // Switch system and reset tries
+ count=1;
+ system=3-system;
+ printf("***Too many boot attempts, switching system***\n");
+ break;
+ default:
+ // Switch system, start over and hope it works
+ printf("***Unexpected data on addr 0x%x, %u***\n",(u32)addr,data);
+ count=1;
+ system=3-system;
+ }
+ }
+ write_bootdata( addr+1, system, count );
+ if(system==SYSTEM_BOOT){
+ failsafe=0;
+ }
+ }
+ }
+ if(failsafe){
+ printf("Booting failsafe system\n");
+ setenv("bootargs","panic=1 root=/dev/hda7");
+ setenv("bootcmd","disk 100000 0:5;bootm 100000");
+ }
+ else{
+ printf("Using normal system\n");
+ setenv("bootargs","panic=1 root=/dev/hda4");
+ setenv("bootcmd","disk 100000 0:2;bootm 100000");
+ }
+}
+
+void misc_init_r(bd_t *bd){
+ u8 Rx[80];
+ u8 Tx[5];
+ int page;
+ int read=0;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+ /* Kill fpga */
+ immap->im_ioport.iop_papar &= ~(PA_FL_CONFIG|PA_FL_CE);
+ immap->im_ioport.iop_padir |= (PA_FL_CONFIG|PA_FL_CE);
+ immap->im_ioport.iop_paodr &= ~(PA_FL_CONFIG|PA_FL_CE);
+
+ /* Enable fpga, active low */
+ immap->im_ioport.iop_padat &= ~PA_FL_CE;
+
+ /* Start configuration */
+ immap->im_ioport.iop_padat &= ~PA_FL_CONFIG;
+ udelay(2);
+
+ immap->im_ioport.iop_padat |= (PA_FL_CONFIG|PA_FL_CE);
+
+ /* Check if we need to boot failsafe system */
+ check_boot_tries();
+
+ if(ee_init_data()){
+ printf("EEPROM init failed\n");
+ return;
+ }
+
+ /* Read the pages where ethernet address is stored */
+
+ for(page=EE_USER_PAGE_0;page<=EE_USER_PAGE_0+2;page++){
+ /* Copy from nvram to scratchpad */
+ Tx[0]=RECALL_MEMORY;
+ Tx[1]=page;
+ if(ee_do_command(Tx,2,NULL,0,TRUE)){
+ printf("EE user page %d recall failed\n",page);
+ return;
+ }
+
+ Tx[0]=READ_SCRATCHPAD;
+ if(ee_do_command(Tx,2,Rx+read,9,TRUE)){
+ printf("EE user page %d read failed\n",page);
+ return;
+ }
+ /* Crc in 9:th byte */
+ if(!ee_crc_ok(Rx+read,8,*(Rx+read+8))){
+ printf("EE read failed, page %d. CRC error\n", page);
+ return;
+ }
+ read+=8;
+ }
+
+ /* Add eos after eth addr*/
+ Rx[17]=0;
+
+ printf("Ethernet addr read from eeprom: %s\n\n",Rx);
+
+ if((Rx[2]!=':')|
+ (Rx[5]!=':')|
+ (Rx[8]!=':')|
+ (Rx[11]!=':')|
+ (Rx[14]!=':')){
+ printf("*** ethernet addr invalid, using default ***\n");
+ }
+ else{
+ setenv("ethaddr",Rx);
+ }
+}
+
+
.plt : { *(.plt) }
.text :
{
+ cpu/mpc8xx/start.o(.text)
*(.text)
common/environment.o(.text)
*(.fixup)
get_env_addr = get_env_addr_memory;
if (idata->env_valid == 0) {
+#if defined(CONFIG_GTH) /* Environment not changable */
+ printf ("Using default environment\n\n");
+#else
+ printf ("*** Warning - bad CRC, using default environment\n\n");
+#endif
/*
* TODO: We should check here that the
* default environment does not overflow the buffer.
*/
- printf ("*** Warning - bad CRC, using default environment\n\n");
memset (env_ptr, 0, sizeof(env_t));
memcpy (env_ptr->data,
default_environment,
#include <command.h>
#include <cmd_nvedit.h>
#include <cmd_bootm.h>
+#if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY)
+#include <cmd_boot.h> /* for do_reset() prototype */
+#endif
static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen);
static int parse_line (char *, char *[]);
/* -2 means timed out, retry autoboot
*/
printf("\nTimed out waiting for command\n");
+# ifdef CONFIG_RESET_TO_RETRY
+ /* Reinit board to run initialization code again */
+ do_reset(NULL,NULL,0,0,NULL);
+# else
return; /* retry autoboot */
+# endif
}
#endif
--- /dev/null
+#include <ppcboot.h>
+#include <commproc.h>
+
+#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
+
+static void UcodeCopy (volatile cpm8xx_t *cpm);
+
+void cpm_load_patch (volatile immap_t *immr)
+{
+ immr->im_cpm.cp_rccr &= ~0x0003; /* Disable microcode program area */
+
+ UcodeCopy ((cpm8xx_t *)&immr->im_cpm); /* Copy ucode patch to DPRAM */
+#ifdef CFG_SPI_UCODE_PATCH
+ {
+ volatile spi_t *spi = (spi_t *) & immr->im_cpm.cp_dparam[PROFF_SPI];
+ /* Activate the microcode per the instructions in the microcode manual */
+ /* NOTE: We're only relocating the SPI parameters (not I2C). */
+ immr->im_cpm.cp_cpmcr1 = 0x802a; /* Write Trap register 1 value */
+ immr->im_cpm.cp_cpmcr2 = 0x8028; /* Write Trap register 2 value */
+ spi->spi_rpbase = CFG_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */
+ }
+#endif
+
+#ifdef CFG_I2C_UCODE_PATCH
+ {
+ volatile iic_t *iip = (iic_t *) & immr->im_cpm.cp_dparam[PROFF_IIC];
+ /* Activate the microcode per the instructions in the microcode manual */
+ /* NOTE: We're only relocating the I2C parameters (not SPI). */
+ immr->im_cpm.cp_cpmcr3 = 0x802e; /* Write Trap register 3 value */
+ immr->im_cpm.cp_cpmcr4 = 0x802c; /* Write Trap register 4 value */
+ iip->iic_rpbase = CFG_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */
+ }
+#endif
+
+ /*
+ * Enable DPRAM microcode to execute from the first 512 bytes
+ * and a 256 byte extension of DPRAM. */
+ */
+ immr->im_cpm.cp_rccr |= 0x0001;
+}
+
+static ulong patch_2000[] = {
+ 0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000,
+ 0x5FEFADF7, 0x5F88ADF7, 0x5FEFAFF7, 0x5F88AFF7,
+ 0x3A9CFBC8, 0x77CAE1BB, 0xF4DE7FAD, 0xABAE9330,
+ 0x4E08FDCF, 0x6E0FAFF8, 0x7CCF76CF, 0xFDAFF9CF,
+ 0xABF88DC8, 0xAB5879F7, 0xB0927383, 0xDFD079F7,
+ 0xB090E6BB, 0xE5BBE74F, 0xB3FA6F0F, 0x6FFB76CE,
+ 0xEE0CF9CF, 0x2BFBEFEF, 0xCFEEF9CF, 0x76CEAD23,
+ 0x90B3DF99, 0x7FDDD0C1, 0x4BF847FD, 0x7CCF76CE,
+ 0xCFEF77CA, 0x7EAF7FAD, 0x7DFDF0B7, 0xEF7A7FCA,
+ 0x77CAFBC8, 0x6079E722, 0xFBC85FFF, 0xDFFF5FB3,
+ 0xFFFBFBC8, 0xF3C894A5, 0xE7C9EDF9, 0x7F9A7FAD,
+ 0x5F36AFE8, 0x5F5BFFDF, 0xDF95CB9E, 0xAF7D5FC3,
+ 0xAFED8C1B, 0x5FC3AFDD, 0x5FC5DF99, 0x7EFDB0B3,
+ 0x5FB3FFFE, 0xABAE5FB3, 0xFFFE5FD0, 0x600BE6BB,
+ 0x600B5FD0, 0xDFC827FB, 0xEFDF5FCA, 0xCFDE3A9C,
+ 0xE7C9EDF9, 0xF3C87F9E, 0x54CA7FED, 0x2D3A3637,
+ 0x756F7E9A, 0xF1CE37EF, 0x2E677FEE, 0x10EBADF8,
+ 0xEFDECFEA, 0xE52F7D9F, 0xE12BF1CE, 0x5F647E9A,
+ 0x4DF8CFEA, 0x5F717D9B, 0xEFEECFEA, 0x5F73E522,
+ 0xEFDE5F73, 0xCFDA0B61, 0x7385DF61, 0xE7C9EDF9,
+ 0x7E9A30D5, 0x1458BFFF, 0xF3C85FFF, 0xDFFFA7F8,
+ 0x5F5BBFFE, 0x7F7D10D0, 0x144D5F33, 0xBFFFAF78,
+ 0x5F5BBFFD, 0xA7F85F33, 0xBFFE77FD, 0x30BD4E08,
+ 0xFDCFE5FF, 0x6E0FAFF8, 0x7EEF7E9F, 0xFDEFF1CF,
+ 0x5F17ABF8, 0x0D5B5F5B, 0xFFEF79F7, 0x309EAFDD,
+ 0x5F3147F8, 0x5F31AFED, 0x7FDD50AF, 0x497847FD,
+ 0x7F9E7FED, 0x7DFD70A9, 0xEF7E7ECE, 0x6BA07F9E,
+ 0x2D227EFD, 0x30DB5F5B, 0xFFFD5F5B, 0xFFEF5F5B,
+ 0xFFDF0C9C, 0xAFED0A9A, 0xAFDD0C37, 0x5F37AFBD,
+ 0x7FBDB081, 0x5F8147F8,
+};
+
+static ulong patch_2F00[] = {
+ 0x3E303430, 0x34343737, 0xABBF9B99, 0x4B4FBDBD,
+ 0x59949334, 0x9FFF37FB, 0x9B177DD9, 0x936956BB,
+ 0xFBDD697B, 0xDD2FD113, 0x1DB9F7BB, 0x36313963,
+ 0x79373369, 0x3193137F, 0x7331737A, 0xF7BB9B99,
+ 0x9BB19795, 0x77FDFD3D, 0x573B773F, 0x737933F7,
+ 0xB991D115, 0x31699315, 0x31531694, 0xBF4FBDBD,
+ 0x35931497, 0x35376956, 0xBD697B9D, 0x96931313,
+ 0x19797937, 0x69350000,
+};
+
+static void UcodeCopy (volatile cpm8xx_t *cpm)
+{
+ vu_long *p;
+ int i;
+
+ p = (vu_long *)&(cpm->cp_dpmem[0x0000]);
+ for (i=0; i < sizeof(patch_2000)/4; ++i) {
+ p[i] = patch_2000[i];
+ }
+
+ p = (vu_long *)&(cpm->cp_dpmem[0x0F00]);
+ for (i=0; i < sizeof(patch_2F00)/4; ++i) {
+ p[i] = patch_2F00[i];
+ }
+}
+
+#endif /* CFG_I2C_UCODE_PATCH, CFG_SPI_UCODE_PATCH */
by hitting a key even in that case when "bootdelay" has been
set to 0. You can set "bootdelay" to a negative value to
prevent the check for console input.
+
+ CONFIG_RESET_TO_RETRY
+
+ (Only effective when CONFIG_BOOT_RETRY_TIME is also set)
+ After the countdown timed out, the board will be reset to restart
+ again.
+
#define CONFIG_MPC860T 1
#define CONFIG_GTH 1
+#define CONFIG_MISC_INIT_R 1
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define MPC8XX_XIN 16384000 /* 16.384 MHz */
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
-#endif
+#define CONFIG_BOOTDELAY 1 /* autoboot after 0 seconds */
+
+#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
-#define CONFIG_BOOT_RETRY_TIME 30 /* Retry boot in 30 secs */
+#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
+
+#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
/* Only interrupt boot if space is pressed */
/* If a long serial cable is connected but */
/* other end is dead, garbage will be read */
#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot\n"
-#define CONFIG_AUTOBOOT_DELAY_STR " "
-#define CONFIG_AUTOBOOT_STOP_STR "s"
+#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
#if 0
/* Net boot */
#define CONFIG_BOOTARGS "panic=1"
#else
/* Compact flash boot */
-#define CONFIG_BOOTARGS "panic=1 root=/dev/hda4"
-#define CONFIG_BOOTCOMMAND "disk 100000 0:2;bootm 100000"
+#define CONFIG_BOOTARGS "panic=1 root=/dev/hda7"
+#define CONFIG_BOOTCOMMAND "disk 100000 0:5;bootm 100000"
#endif
-#undef CONFIG_WATCHDOG
-/* #define CONFIG_WATCHDOG 1 / * watchdog disabled */
+/* Enable watchdog */
+#define CONFIG_WATCHDOG 1
/* choose SCC1 ethernet (10BASET on motherboard)
* or FEC ethernet (10/100 on daughterboard)
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#ifndef CONFIG_START_IN_RAM
-#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#else
-#define CFG_MONITOR_BASE 0
-#endif
+#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
#define CFG_ENV_IS_IN_FLASH 1
#undef CFG_ENV_IS_IN_EEPROM
-#define CFG_ENV_OFFSET 0x00080000
+#define CFG_ENV_OFFSET 0x000E0000
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
+#define CFG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */
/*-----------------------------------------------------------------------
* Cache Configuration
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
#define PA_FRONT_LED ((u16)0x4) /* PA 13 */
+#define PA_FL_CONFIG ((u16)0x20) /* PA 10 */
+#define PA_FL_CE ((u16)0x1000) /* PA 3 */
#define PB_ID_GND ((u32)1) /* PB 31 */
#define PB_REV_1 ((u32)2) /* PB 30 */
#define PB_ID_1 ((u32)0x8000) /* PB 16 */
#define PB_ID_0 ((u32)0x10000) /* PB 15 */
+/* NOTE. This is reset for 100Mbit port only */
+#define PC_ENET100_RESET ((ushort)0x0080) /* PC 8 */
+
#endif /* __CONFIG_H */
projects / users / rw / ppcboot.git / commitdiff