drm/i915: Engage the DP scramble reset for pipe C on CHV

To get stable CRCs from the DP CRC source we need to reset the
scrambler for each frame. Enable the reset feature when grabbing
CRCs for pipe C on CHV. Pipes A and B were already covered due
sharing the code with VLV.

We can safely extend PIPE_SCRAMBLE_RESET_MASK to deal with CHV since
the extra bit was MBZ on the older platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d0e445eca9ce5fbee6a4b18fd903ca302b541730..d74b62d0ec72fb6258cf859a9583bdb991014a6b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3120,11 +3120,19 @@ static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
                uint32_t tmp = I915_READ(PORT_DFT2_G4X);
 
                tmp |= DC_BALANCE_RESET_VLV;
-               if (pipe == PIPE_A)
+               switch (pipe) {
+               case PIPE_A:
                        tmp |= PIPE_A_SCRAMBLE_RESET;
-               else
+                       break;
+               case PIPE_B:
                        tmp |= PIPE_B_SCRAMBLE_RESET;
-
+                       break;
+               case PIPE_C:
+                       tmp |= PIPE_C_SCRAMBLE_RESET;
+                       break;
+               default:
+                       return -EINVAL;
+               }
                I915_WRITE(PORT_DFT2_G4X, tmp);
        }
 
@@ -3213,10 +3221,19 @@ static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
        struct drm_i915_private *dev_priv = dev->dev_private;
        uint32_t tmp = I915_READ(PORT_DFT2_G4X);
 
-       if (pipe == PIPE_A)
+       switch (pipe) {
+       case PIPE_A:
                tmp &= ~PIPE_A_SCRAMBLE_RESET;
-       else
+               break;
+       case PIPE_B:
                tmp &= ~PIPE_B_SCRAMBLE_RESET;
+               break;
+       case PIPE_C:
+               tmp &= ~PIPE_C_SCRAMBLE_RESET;
+               break;
+       default:
+               return;
+       }
        if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
                tmp &= ~DC_BALANCE_RESET_VLV;
        I915_WRITE(PORT_DFT2_G4X, tmp);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aa628998f83601ad1a9091d229721bf02565a362..451d526ea5d548ff802d5aaac0cb7792da9df0c4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2789,7 +2789,8 @@ enum punit_power_well {
 #define   DC_BALANCE_RESET                     (1 << 25)
 #define PORT_DFT2_G4X          (dev_priv->info.display_mmio_offset + 0x61154)
 #define   DC_BALANCE_RESET_VLV                 (1 << 31)
-#define   PIPE_SCRAMBLE_RESET_MASK             (0x3 << 0)
+#define   PIPE_SCRAMBLE_RESET_MASK             ((1 << 14) | (0x3 << 0))
+#define   PIPE_C_SCRAMBLE_RESET                        (1 << 14) /* chv */
 #define   PIPE_B_SCRAMBLE_RESET                        (1 << 1)
 #define   PIPE_A_SCRAMBLE_RESET                        (1 << 0)