net: ethernet: ti: cpsw_ale: add Policer and Thread control register fields

Adds regfileds for Policer registers and Thread mapping/control registers.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c
index 9e45470b4eb94f000070428aa5078132945dfab0..aafe1210de52c493f584d9b03f16b288d8027417 100644 (file)
--- a/drivers/net/ethernet/ti/cpsw_ale.c
+++ b/drivers/net/ethernet/ti/cpsw_ale.c
@@ -46,6 +46,24 @@
 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS     0x9C
 #define ALE_VLAN_MASK_MUX(reg)                 (0xc0 + (0x4 * (reg)))
 
+#define ALE_POLICER_PORT_OUI           0x100
+#define ALE_POLICER_DA_SA              0x104
+#define ALE_POLICER_VLAN               0x108
+#define ALE_POLICER_ETHERTYPE_IPSA     0x10c
+#define ALE_POLICER_IPDA               0x110
+#define ALE_POLICER_PIR                        0x118
+#define ALE_POLICER_CIR                        0x11c
+#define ALE_POLICER_TBL_CTL            0x120
+#define ALE_POLICER_CTL                        0x124
+#define ALE_POLICER_TEST_CTL           0x128
+#define ALE_POLICER_HIT_STATUS         0x12c
+#define ALE_THREAD_DEF                 0x134
+#define ALE_THREAD_CTL                 0x138
+#define ALE_THREAD_VAL                 0x13c
+
+#define ALE_POLICER_TBL_WRITE_ENABLE   BIT(31)
+#define ALE_POLICER_TBL_INDEX_MASK     GENMASK(4, 0)
+
 #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134
 
 /* ALE_AGING_TIMER */
@@ -1306,6 +1324,74 @@ static const struct reg_field ale_fields_cpsw_nu[] = {
        /* CPSW_ALE_STATUS_REG */
        [ALE_ENTRIES]   = REG_FIELD(ALE_STATUS, 0, 7),
        [ALE_POLICERS]  = REG_FIELD(ALE_STATUS, 8, 15),
+       /* CPSW_ALE_POLICER_PORT_OUI_REG */
+       [POL_PORT_MEN]  = REG_FIELD(ALE_POLICER_PORT_OUI, 31, 31),
+       [POL_TRUNK_ID]  = REG_FIELD(ALE_POLICER_PORT_OUI, 30, 30),
+       [POL_PORT_NUM]  = REG_FIELD(ALE_POLICER_PORT_OUI, 25, 25),
+       [POL_PRI_MEN]   = REG_FIELD(ALE_POLICER_PORT_OUI, 19, 19),
+       [POL_PRI_VAL]   = REG_FIELD(ALE_POLICER_PORT_OUI, 16, 18),
+       [POL_OUI_MEN]   = REG_FIELD(ALE_POLICER_PORT_OUI, 15, 15),
+       [POL_OUI_INDEX] = REG_FIELD(ALE_POLICER_PORT_OUI, 0, 5),
+
+       /* CPSW_ALE_POLICER_DA_SA_REG */
+       [POL_DST_MEN]   = REG_FIELD(ALE_POLICER_DA_SA, 31, 31),
+       [POL_DST_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 16, 21),
+       [POL_SRC_MEN]   = REG_FIELD(ALE_POLICER_DA_SA, 15, 15),
+       [POL_SRC_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 0, 5),
+
+       /* CPSW_ALE_POLICER_VLAN_REG */
+       [POL_OVLAN_MEN]         = REG_FIELD(ALE_POLICER_VLAN, 31, 31),
+       [POL_OVLAN_INDEX]       = REG_FIELD(ALE_POLICER_VLAN, 16, 21),
+       [POL_IVLAN_MEN]         = REG_FIELD(ALE_POLICER_VLAN, 15, 15),
+       [POL_IVLAN_INDEX]       = REG_FIELD(ALE_POLICER_VLAN, 0, 5),
+
+       /* CPSW_ALE_POLICER_ETHERTYPE_IPSA_REG */
+       [POL_ETHERTYPE_MEN]     = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 31, 31),
+       [POL_ETHERTYPE_INDEX]   = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 16, 21),
+       [POL_IPSRC_MEN]         = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 15, 15),
+       [POL_IPSRC_INDEX]       = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 0, 5),
+
+       /* CPSW_ALE_POLICER_IPDA_REG */
+       [POL_IPDST_MEN]         = REG_FIELD(ALE_POLICER_IPDA, 31, 31),
+       [POL_IPDST_INDEX]       = REG_FIELD(ALE_POLICER_IPDA, 16, 21),
+
+       /* CPSW_ALE_POLICER_TBL_CTL_REG */
+       /**
+        * REG_FIELDS not defined for this as fields cannot be correctly
+        * used independently
+        */
+
+       /* CPSW_ALE_POLICER_CTL_REG */
+       [POL_EN]                = REG_FIELD(ALE_POLICER_CTL, 31, 31),
+       [POL_RED_DROP_EN]       = REG_FIELD(ALE_POLICER_CTL, 29, 29),
+       [POL_YELLOW_DROP_EN]    = REG_FIELD(ALE_POLICER_CTL, 28, 28),
+       [POL_YELLOW_THRESH]     = REG_FIELD(ALE_POLICER_CTL, 24, 26),
+       [POL_POL_MATCH_MODE]    = REG_FIELD(ALE_POLICER_CTL, 22, 23),
+       [POL_PRIORITY_THREAD_EN] = REG_FIELD(ALE_POLICER_CTL, 21, 21),
+       [POL_MAC_ONLY_DEF_DIS]  = REG_FIELD(ALE_POLICER_CTL, 20, 20),
+
+       /* CPSW_ALE_POLICER_TEST_CTL_REG */
+       [POL_TEST_CLR]          = REG_FIELD(ALE_POLICER_TEST_CTL, 31, 31),
+       [POL_TEST_CLR_RED]      = REG_FIELD(ALE_POLICER_TEST_CTL, 30, 30),
+       [POL_TEST_CLR_YELLOW]   = REG_FIELD(ALE_POLICER_TEST_CTL, 29, 29),
+       [POL_TEST_CLR_SELECTED] = REG_FIELD(ALE_POLICER_TEST_CTL, 28, 28),
+       [POL_TEST_ENTRY]        = REG_FIELD(ALE_POLICER_TEST_CTL, 0, 4),
+
+       /* CPSW_ALE_POLICER_HIT_STATUS_REG */
+       [POL_STATUS_HIT]        = REG_FIELD(ALE_POLICER_HIT_STATUS, 31, 31),
+       [POL_STATUS_HIT_RED]    = REG_FIELD(ALE_POLICER_HIT_STATUS, 30, 30),
+       [POL_STATUS_HIT_YELLOW] = REG_FIELD(ALE_POLICER_HIT_STATUS, 29, 29),
+
+       /* CPSW_ALE_THREAD_DEF_REG */
+       [ALE_DEFAULT_THREAD_EN]         = REG_FIELD(ALE_THREAD_DEF, 15, 15),
+       [ALE_DEFAULT_THREAD_VAL]        = REG_FIELD(ALE_THREAD_DEF, 0, 5),
+
+       /* CPSW_ALE_THREAD_CTL_REG */
+       [ALE_THREAD_CLASS_INDEX] = REG_FIELD(ALE_THREAD_CTL, 0, 4),
+
+       /* CPSW_ALE_THREAD_VAL_REG */
+       [ALE_THREAD_ENABLE]     = REG_FIELD(ALE_THREAD_VAL, 15, 15),
+       [ALE_THREAD_VALUE]      = REG_FIELD(ALE_THREAD_VAL, 0, 5),
 };
 
 static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = {

diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h
index e12bb2caf016247bcdfc10cf532fd600f22314ce..2cb76acc6d16910fad5fdf991f5bf48767b37379 100644 (file)
--- a/drivers/net/ethernet/ti/cpsw_ale.h
+++ b/drivers/net/ethernet/ti/cpsw_ale.h
@@ -36,6 +36,47 @@ enum ale_fields {
        MAJOR_VER,
        ALE_ENTRIES,
        ALE_POLICERS,
+       POL_PORT_MEN,
+       POL_TRUNK_ID,
+       POL_PORT_NUM,
+       POL_PRI_MEN,
+       POL_PRI_VAL,
+       POL_OUI_MEN,
+       POL_OUI_INDEX,
+       POL_DST_MEN,
+       POL_DST_INDEX,
+       POL_SRC_MEN,
+       POL_SRC_INDEX,
+       POL_OVLAN_MEN,
+       POL_OVLAN_INDEX,
+       POL_IVLAN_MEN,
+       POL_IVLAN_INDEX,
+       POL_ETHERTYPE_MEN,
+       POL_ETHERTYPE_INDEX,
+       POL_IPSRC_MEN,
+       POL_IPSRC_INDEX,
+       POL_IPDST_MEN,
+       POL_IPDST_INDEX,
+       POL_EN,
+       POL_RED_DROP_EN,
+       POL_YELLOW_DROP_EN,
+       POL_YELLOW_THRESH,
+       POL_POL_MATCH_MODE,
+       POL_PRIORITY_THREAD_EN,
+       POL_MAC_ONLY_DEF_DIS,
+       POL_TEST_CLR,
+       POL_TEST_CLR_RED,
+       POL_TEST_CLR_YELLOW,
+       POL_TEST_CLR_SELECTED,
+       POL_TEST_ENTRY,
+       POL_STATUS_HIT,
+       POL_STATUS_HIT_RED,
+       POL_STATUS_HIT_YELLOW,
+       ALE_DEFAULT_THREAD_EN,
+       ALE_DEFAULT_THREAD_VAL,
+       ALE_THREAD_CLASS_INDEX,
+       ALE_THREAD_ENABLE,
+       ALE_THREAD_VALUE,
        /* terminator */
        ALE_FIELDS_MAX,
 };