* Completed support for CU824 board
+* Add FPGA download for PCU E configuration
+
* Fixed PCU E configuration for other / bigger flash types
-* Cleanup of C++ style // comments which cause C compiler warnings.
+* Cleanup of C++ style // comments which cause C compiler warnings
======================================================================
Modifications for 0.9.2:
#endif /* CFG_CMD_BSP */
/*-----------------------------------------------------------------------
- * Test: Enable Ethernet
+ * Utilities
*/
uchar pic_read (uchar reg)
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
+static void puma_status (void);
+static void puma_set_mode (int mode);
+static int puma_init_done (void);
+static void puma_load (ulong addr, ulong len);
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
+/*
+ * PUMA access using UPM B
+ */
+const uint puma_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPM RAM)
+ */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_,
+ /*
+ * Precharge and MRS
+ */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Read. (Offset 8 in UPM RAM)
+ */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPM RAM)
+ */
+ 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPM RAM)
+ */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPM RAM)
+ */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPM RAM)
+ */
+ 0x7ffffc07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
/*
* Check Board Identity:
/*
* Map controller bank 2 to the SDRAM bank at preliminary address.
*/
- //memctl->memc_or2 = CFG_OR2_PRELIM;
- //memctl->memc_br2 = CFG_BR2_PRELIM;
- memctl->memc_or5 = CFG_OR5_PRELIM; /* XXX Test Board only XXX */
- memctl->memc_br5 = CFG_BR5_PRELIM; /* XXX Test Board only XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+ memctl->memc_or5 = CFG_OR5_PRELIM;
+ memctl->memc_br5 = CFG_BR5_PRELIM;
+#else /* XXX */
+ memctl->memc_or2 = CFG_OR2_PRELIM;
+ memctl->memc_br2 = CFG_BR2_PRELIM;
+#endif /* XXX */
/* initialize memory address register */
memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
/* mode initialization (offset 5) */
-// udelay(200); /* 0x80004105 */
-// memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05);
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay(200); /* 0x8000A105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x05);
+#else /* XXX */
+ udelay(200); /* 0x80004105 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05);
+#endif /* XXX */
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
-// udelay(1); /* 0x80004830 */
-// memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30);
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay(1); /* 0x8000A830 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(8) | MCR_MAD(0x30);
+#else /* XXX */
+ udelay(1); /* 0x80004830 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30);
+#endif /* XXX */
-// udelay(1); /* 0x80004106 */
-// memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06);
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay(1); /* 0x8000A106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x06);
+#else /* XXX */
+ udelay(1); /* 0x80004106 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06);
+#endif /* XXX */
reg = memctl->memc_mamr;
reg &= ~MAMR_TLFB_MSK; /* switch timer loop ... */
/* Need at least 10 DRAM accesses to stabilize */
for (i=0; i<10; ++i) {
-// volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM;
+#else /* XXX */
+ volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
+#endif /* XXX */
unsigned long val;
val = *(addr + i);
/*
* Check Bank 0 Memory Size for re-configuration
*/
-// size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
+#else /* XXX */
+ size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+#endif /* XXX */
memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
* Final mapping:
*/
- //memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
- //memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-/* XXX Test Board only XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-/* XXX Test Board only XXX */
+#else /* XXX */
+ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
+ memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+#endif /* XXX */
udelay(1000);
+ /*
+ * Configure UPMB for PUMA
+ */
+ upmconfig(UPMB, (uint *)puma_table, sizeof(puma_table)/sizeof(uint));
+
return (size_b0);
}
/* ------------------------------------------------------------------------- */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
+#else /* XXX */
#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
+#endif /* XXX */
#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
ulong value;
/* Configure all needed port pins for GPIO */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+# if CFG_ETH_MDDIS_VALUE
+ immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
+# else
+ immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
+# endif
+ immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */
+ immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */
+ immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
+#endif /* XXX */
immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
value &= ~(CFG_PB_ETH_RESET);
/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
-#if CFG_PB_ETH_MDDIS_VALUE
+#if !PCU_E_WITH_SWAPPED_CS
+# if CFG_ETH_MDDIS_VALUE
value |= CFG_PB_ETH_MDDIS;
-#else
+# else
value &= ~(CFG_PB_ETH_MDDIS);
+# endif
#endif
-#if CFG_PB_ETH_CFG1_VALUE
+#if CFG_ETH_CFG1_VALUE
value |= CFG_PB_ETH_CFG1;
#else
value &= ~(CFG_PB_ETH_CFG1);
#endif
-#if CFG_PB_ETH_CFG2_VALUE
+#if CFG_ETH_CFG2_VALUE
value |= CFG_PB_ETH_CFG2;
#else
value &= ~(CFG_PB_ETH_CFG2);
#endif
-#if CFG_PB_ETH_CFG3_VALUE
+#if CFG_ETH_CFG3_VALUE
value |= CFG_PB_ETH_CFG3;
#else
value &= ~(CFG_PB_ETH_CFG3);
udelay (1000);
}
+/*-----------------------------------------------------------------------
+ * Board Special Commands: access functions for "PUMA" FPGA
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+#define PUMA_READ_MODE 0
+#define PUMA_LOAD_MODE 1
+
+void do_puma (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ ulong addr, len;
+
+ switch (argc) {
+ case 2: /* PUMA reset */
+ if (strncmp(argv[1], "stat", 4) == 0) { /* Reset */
+ puma_status ();
+ return;
+ }
+ break;
+ case 4: /* PUMA load addr len */
+ if (strcmp(argv[1],"load") != 0)
+ break;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+ len = simple_strtoul(argv[3], NULL, 16);
+
+ printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
+ addr, len, len);
+ puma_load (addr, len);
+
+ return;
+ default:
+ break;
+ }
+ printf ("Usage:\n%s\n", cmdtp->usage);
+}
+
+#endif /* CFG_CMD_BSP */
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static void puma_set_mode (int mode)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+ /* disable PUMA in memory controller */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+ memctl->memc_br3 = 0;
+#else /* XXX */
+ memctl->memc_br4 = 0;
+#endif /* XXX */
+
+ switch (mode) {
+ case PUMA_READ_MODE:
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+ memctl->memc_or3 = PUMA_CONF_OR_READ;
+ memctl->memc_br3 = PUMA_CONF_BR_READ;
+#else /* XXX */
+ memctl->memc_or4 = PUMA_CONF_OR_READ;
+ memctl->memc_br4 = PUMA_CONF_BR_READ;
+#endif /* XXX */
+ break;
+ case PUMA_LOAD_MODE:
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+ memctl->memc_or3 = PUMA_CONF_OR_LOAD;
+ memctl->memc_br3 = PUMA_CONF_BR_LOAD;
+#else /* XXX */
+ memctl->memc_or4 = PUMA_CONF_OR_READ;
+ memctl->memc_br4 = PUMA_CONF_BR_READ;
+#endif /* XXX */
+ break;
+ }
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
+
+static void puma_load (ulong addr, ulong len)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */
+ uchar *data = (uchar *)addr;
+ int i;
+
+ /* align length */
+ if (len & 1)
+ ++len;
+
+ /* Reset FPGA */
+ immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */
+ immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT);
+ immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+ immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */
+ immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */
+ immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */
+ immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */
+#else
+ immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */
+ immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */
+ immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */
+ immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */
+#endif /* XXX */
+ udelay (100);
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+ immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
+#else
+ immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
+#endif /* XXX */
+
+ /* wait until INIT indicates completion of reset */
+ for (i=0; i<PUMA_INIT_TIMEOUT; ++i) {
+ udelay (1000);
+ if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
+ break;
+ }
+ if (i == PUMA_INIT_TIMEOUT) {
+ printf ("*** PUMA init timeout ***\n");
+ return;
+ }
+
+ puma_set_mode (PUMA_LOAD_MODE);
+
+ while (len--)
+ *fpga_addr = *data++;
+
+ puma_set_mode (PUMA_READ_MODE);
+
+ puma_status ();
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static void puma_status (void)
+{
+ /* Check state */
+ printf ("PUMA initialization is %scomplete\n",
+ puma_init_done() ? "" : "NOT ");
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static int puma_init_done (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ /* make sure pin is GPIO input */
+ immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
+ immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
+ immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
+
+ return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void misc_init_r (bd_t *dummy)
+{
+ ulong addr = 0;
+ ulong len = 0;
+ char *s;
+
+ printf (" PUMA: ");
+ if (puma_init_done()) {
+ printf ("initialized\n");
+ return;
+ }
+
+ if ((s = getenv("puma_addr")) != NULL)
+ addr = simple_strtoul(s, NULL, 16);
+
+ if ((s = getenv("puma_len")) != NULL)
+ len = simple_strtoul(s, NULL, 16);
+
+ if ((!addr) || (!len)) {
+ printf ("net list undefined\n");
+ return;
+ }
+
+ printf ("loading... ");
+
+ puma_load (addr, len);
+}
+
/* ------------------------------------------------------------------------- */
/* relocate environment function pointers etc. */
env_relocate (reloc_off);
-#if defined(CONFIG_COGENT) || defined(CONFIG_HYMOD) || defined(CONFIG_CPCI405)
+#if defined(CONFIG_COGENT) || \
+ defined(CONFIG_HYMOD) || \
+ defined(CONFIG_CPCI405) || \
+ defined(CONFIG_PCU_E)
/* miscellaneous platform dependent initialisations */
misc_init_r(bd);
#endif
#endif /* CONFIG_LWMON */
/* ----------------------------------------------------------------------------*/
+/* ----- PCU E -----------------------------------------------------------------
+ */
+#if defined(CONFIG_PCU_E)
+
+#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \
+ "puma", 4, 4, 1, do_puma, \
+ "puma - access PUMA FPGA\n", \
+ "status - print PUMA status\n" \
+ "puma load addr len - load PUMA configuration data\n" \
+),
+
+void do_puma (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+
+#endif /* CONFIG_PCU_E */
+/* ----------------------------------------------------------------------------*/
+
#else
#define CMD_TBL_BSP
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_ETHADDR 08:00:22:50:70:63 // Ethernet address
-#define CONFIG_ENV_OVERWRITE 1 // Overwrite the environment
+#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
+#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
-#define CONFIG_VIDEO 1 // To enable video controller support
-#define CONFIG_I2C 1 // To enable I2C support
-//Now included by CFG_CMD_PCMCIA
-//#define CONFIG_PCMCIA 1 // To enable PCMCIA support
+#define CONFIG_VIDEO 1 /* To enable video controller support */
+#define CONFIG_I2C 1 /* To enable I2C support */
+/*Now included by CFG_CMD_PCMCIA */
+/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
/* Video related */
-#define CONFIG_VIDEO_LOGO 1 // Show the logo
-#define CONFIG_VIDEO_ENCODER_AD7176 1 // Enable this encoder
-#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 // Default on fads
+#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
+#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
+#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
#define CONFIG_VIDEO_SIZE (2*1024*1024)
-#define CONFIG_VIDEO_ADDR (bd_ptr->bi_memsize - CONFIG_VIDEO_SIZE) // Frame buffer address
+#define CONFIG_VIDEO_ADDR (bd_ptr->bi_memsize - CONFIG_VIDEO_SIZE) /* Frame buffer address */
/* Wireless 56Khz 4PPM keyboard on SMCx */
-//#define CONFIG_WL_4PPM_KEYBOARD 1
-#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 // SMC to use (0 indexed)
+/*#define CONFIG_WL_4PPM_KEYBOARD 1 */
+#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
/*
* High Level Configuration Options
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200
-// Set the CPU speed to 50Mhz on the FADS
+/* Set the CPU speed to 50Mhz on the FADS */
#if 0
#define MPC8XX_FACT 10 /* Multiply by 10 */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_ETHADDR 08:00:22:50:70:63 // Ethernet address
-#define CONFIG_ENV_OVERWRITE 1 // Overwrite the environment
+#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
+#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
-#define CFG_ALLOC_DPRAM // Use dynamic DPRAM allocation
+#define CFG_ALLOC_DPRAM /* Use dynamic DPRAM allocation */
-#define CFG_AUTOLOAD "n" // No autoload
+#define CFG_AUTOLOAD "n" /* No autoload */
-//#define CONFIG_VIDEO 1 // To enable the video initialization
-//#define CONFIG_VIDEO_ADDR 0x00200000
-//#define CONFIG_I2C 1 // Needed for 7176 & 7177
-//#define CONFIG_PCMCIA 1 // To enable the PCMCIA initialization
+/*#define CONFIG_VIDEO 1 // To enable the video initialization */
+/*#define CONFIG_VIDEO_ADDR 0x00200000 */
+/*#define CONFIG_I2C 1 // Needed for 7176 & 7177 */
+/*#define CONFIG_PCMCIA 1 // To enable the PCMCIA initialization */
-//#define CFG_PCMCIA_IO_ADDR 0xff020000
-//#define CFG_PCMCIA_IO_SIZE 0x10000
-//#define CFG_PCMCIA_MEM_ADDR 0xe0000000
-//#define CFG_PCMCIA_MEM_SIZE 0x10000
+/*#define CFG_PCMCIA_IO_ADDR 0xff020000 */
+/*#define CFG_PCMCIA_IO_SIZE 0x10000 */
+/*#define CFG_PCMCIA_MEM_ADDR 0xe0000000 */
+/*#define CFG_PCMCIA_MEM_SIZE 0x10000 */
/* Video related */
-//#define CONFIG_VIDEO_LOGO 1 // Show the logo
-//#define CONFIG_VIDEO_ENCODER_AD7177 1 // Enable this encoder
-//#define CONFIG_VIDEO_ENCODER_AD7177_ADDR 0xF4 // ALSB to ground
+/*#define CONFIG_VIDEO_LOGO 1 // Show the logo */
+/*#define CONFIG_VIDEO_ENCODER_AD7177 1 // Enable this encoder */
+/*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR 0xF4 // ALSB to ground */
/* Wireless 56Khz 4PPM keyboard on SMCx */
-//#define CONFIG_WL_4PPM_KEYBOARD 0
-//#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 // SMC to use (0 indexed)
+/*#define CONFIG_WL_4PPM_KEYBOARD 0 */
+/*#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 // SMC to use (0 indexed) */
/*
* High Level Configuration Options
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
OR_SCY_15_CLK | OR_TRLX )
-//#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) // 0xfff80ff4
-#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) // 0x02800401
+/*#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) */
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */
/*
* BR1/2 and OR1/2 (SDRAM)
#define CFG_OR_TIMING_SDRAM 0x00000A00
-#define SDRAM_MAX_SIZE 0x04000000 // 64Mb bank
-#define SDRAM_BASE1_PRELIM 0x00000000 // First bank
-#define SDRAM_BASE2_PRELIM 0x10000000 // Second bank
+#define SDRAM_MAX_SIZE 0x04000000 /* 64Mb bank */
+#define SDRAM_BASE1_PRELIM 0x00000000 /* First bank */
+#define SDRAM_BASE2_PRELIM 0x10000000 /* Second bank */
/*
* Memory Periodic Timer Prescaler
/* 8 column SDRAM */
#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \
- | MAMR_TLFA_4X) // 0x5d802114
+ | MAMR_TLFA_4X) /* 0x5d802114 */
/*
* Internal Definitions
#define CONFIG_BOOT_RETRY_TIME 30 /* Retry boot in 30 secs */
-// Only interrupt boot if space is pressed
-// If a long serial cable is connected but
-// other end is dead, garbage will be read
+/* Only interrupt boot if space is pressed */
+/* If a long serial cable is connected but */
+/* other end is dead, garbage will be read */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot\n"
#define CONFIG_AUTOBOOT_DELAY_STR " "
#define CONFIG_AUTOBOOT_STOP_STR "s"
#if 0
-// Net boot
+/* Net boot */
/* Loads a tftp image and starts it */
#define CONFIG_BOOTCOMMAND "bootp;bootm 100000" /* autoboot command */
#define CONFIG_BOOTARGS "panic=1"
#else
-// Compact flash boot
+/* Compact flash boot */
#define CONFIG_BOOTARGS "panic=1 root=/dev/hda4"
#define CONFIG_BOOTCOMMAND "disk 100000 0:2;bootm 100000"
#endif
#undef CONFIG_WATCHDOG
-// #define CONFIG_WATCHDOG 1 /* watchdog disabled */
+/* #define CONFIG_WATCHDOG 1 / * watchdog disabled */
/* choose SCC1 ethernet (10BASET on motherboard)
* or FEC ethernet (10/100 on daughterboard)
*-----------------------------------------------------------------------
*/
-//FIXME dont use for now
-//#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-//#define CFG_RTCSC (RTCSC_RTF)
+/*FIXME dont use for now */
+/*#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+/*#define CFG_RTCSC (RTCSC_RTF) */
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
-// PITE
+/* PITE */
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* power management and some other internal clocks
*/
-// FIXME check values
+/* FIXME check values */
#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR (SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFC00000
-//%%% #define CFG_FLASH_BASE 0xFFF00000
+/*%%% #define CFG_FLASH_BASE 0xFFF00000 */
#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#endif
#define CFG_MONITOR_BASE 0xFFF00000
-//%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE
+/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
-//%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
/*-----------------------------------------------------------------------
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-// Configuration variable added by yooth.
-//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
+/* Configuration variable added by yooth. */
+/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
/*
* BCSRx
#define CONFIG_RESET_ON_PANIC /* reset if system panic() */
-// to put environment in EEROM
+/* to put environment in EEROM */
#define CFG_ENV_IS_IN_EEPROM 1
#define CFG_ENV_OFFSET 0 /* Start right at beginning of NVRAM */
#define CFG_ENV_SIZE 512 /* Use only a part of it*/
*-----------------------------------------------------------------------
* +0x0000 => 0x000000C0
*/
-#define CFG_SIUMCR 0 //XXX-wd-XXX (SIUMCR_BSC | SIUMCR_GB5E)
+#define CFG_SIUMCR 0
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
#define CONFIG_MPC823 1 /* This is a MPC823E CPU */
#define CONFIG_LWMON 1 /* ...on a LWMON board */
+#if 1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-//#define CONFIG_8xx_CONS_SCC2
+#else
+#define CONFIG_8xx_CONS_SCC2
+#endif
#define CONFIG_BAUDRATE 19200
#if 0
/* EARB, DBGC and DBPC are initialised by the HCW */
/* => 0x000000C0 */
#define CFG_SIUMCR (SIUMCR_GB5E)
-//#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+/*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
#ifndef __CONFIG_H
#define __CONFIG_H
+/*
+ * Workaround for layout bug on prototype board
+ */
+#define PCU_E_WITH_SWAPPED_CS 1
+
/*
* High Level Configuration Options
* (easy to change)
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE | CFG_CMD_BSP)
#define CONFIG_BOOTP_MASK \
((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
/* Ethernet hardware configuration done using port pins */
-#define CFG_PB_ETH_MDDIS 0x00000010 /* PB 27 */
#define CFG_PB_ETH_RESET 0x00000020 /* PB 26 */
-#if 0 /* XXX */
-#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
-#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */
-#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */
-#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */
-#else /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */
#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */
#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */
#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */
+#else /* XXX */
+#define CFG_PB_ETH_MDDIS 0x00000010 /* PB 27 */
+#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
+#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */
+#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */
+#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */
#endif /* XXX */
/* Ethernet settings:
* MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
*/
-#define CFG_PB_ETH_MDDIS_VALUE 0
-#define CFG_PB_ETH_CFG1_VALUE 1
-#define CFG_PB_ETH_CFG2_VALUE 1
-#define CFG_PB_ETH_CFG3_VALUE 1
+#define CFG_ETH_MDDIS_VALUE 0
+#define CFG_ETH_CFG1_VALUE 1
+#define CFG_ETH_CFG2_VALUE 1
+#define CFG_ETH_CFG3_VALUE 1
+
+/* PUMA configuration */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_PB_PUMA_PROG 0x00000010 /* PB 27 */
+#else /* XXX */
+#define CFG_PA_PUMA_PROG 0x4000 /* PA 1 */
+#endif /* XXX */
+#define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */
+#define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
*/
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
-#if 0 /* XXX */
-#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */
-#else /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */
+#else /* XXX */
+#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */
#endif /* XXX */
/*
/* 16 bit, bank valid */
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#if 0 /* XXX */
-#define CFG_OR1_REMAP CFG_OR0_REMAP
-#define CFG_OR1_PRELIM CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#else /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
#define CFG_OR6_REMAP CFG_OR0_REMAP
#define CFG_OR6_PRELIM CFG_OR0_PRELIM
#define CFG_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#else /* XXX */
+#define CFG_OR1_REMAP CFG_OR0_REMAP
+#define CFG_OR1_PRELIM CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
#endif /* XXX */
/*
*
* Multiplexed addresses, GPL5 output to GPL5_A (don't care)
*/
-#if 0 /* XXX */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */
-#else /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */
+#else /* XXX */
+#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */
#endif /* XXX */
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */
#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-#if 0 /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CFG_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else /* XXX */
#define CFG_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#endif /* XXX */
+
+/*
+ * BR3/OR3: CAN Controller
+ */
+#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */
+#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */
+/* ??? */
+
+/*
+ * BR4/OR4: PUMA Config
+ *
+ * Memory controller will be used in 2 modes:
+ *
+ * - "read" mode:
+ * BR4: 0x10100801 OR4: 0xffff8520
+ * - "load" mode (chip select on UPM B):
+ * BR4: 0x101008c1 OR4: 0xffff8600
+ *
+ * Default initialization is in "read" mode
+ */
+#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
+#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
+#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2)
+#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_2_CLK)
+
+#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
+ BR_PS_16 | BR_MS_UPMB | BR_V)
+#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
+
+#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_BR3_PRELIM PUMA_CONF_BR_READ
+#define CFG_OR3_PRELIM PUMA_CONF_OR_READ
#else /* XXX */
-#define CFG_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CFG_BR4_PRELIM PUMA_CONF_BR_READ
+#define CFG_OR4_PRELIM PUMA_CONF_OR_READ
#endif /* XXX */
+/*
+ * BR5/OR5: PUMA: SMA Bus 8 Bit
+ */
+#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
+#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
+
+/*
+ * BR6/OR6: PUMA: SMA Bus 16 Bit
+ */
+#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
+#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
+
+/*
+ * BR7/OR7: PUMA: external Flash
+ */
+#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
+#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
+
/*
* Memory Periodic Timer Prescaler
*/
#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
-//#define PHYS_DPRAM_PCI_SEM 0x04020000 /* DPRAM PPC/PCI Semaphore */
-//#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 /* 1 Byte */
+/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */
+/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */
#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
-//#define PHYS_DPRAM_SHARC_SEM 0x04140000 /* DPRAM PPC/Sharc Semaphore */
-//#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 /* 1 Byte */
+/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */
+/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */
#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
*/
#define CFG_SDRAM_BASE PHYS_SDRAM_60X
#define CFG_FLASH_BASE PHYS_FLASH
-//#define CFG_MONITOR_BASE 0x200000
+/*#define CFG_MONITOR_BASE 0x200000 */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#if CFG_MONITOR_BASE < CFG_FLASH_BASE
#define CFG_RAMBOOT
void pciinfo (int);
#endif
-#if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T) || \
- defined(CONFIG_RSD_PROTO) || defined(CONFIG_HYMOD) || \
- defined(CONFIG_CPCI405)
+#if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T) || \
+ defined(CONFIG_RSD_PROTO) || defined(CONFIG_HYMOD) || \
+ defined(CONFIG_CPCI405) || defined(CONFIG_PCU_E)
/* cogent - $(BOARD)/mb.c */
/* SXNI855T and HYMOD - $(BOARD)/$(BOARD).c */
+# ifndef CONFIG_PCU_E
int misc_init_f (void);
+# endif
void misc_init_r (bd_t *);
#endif
#ifndef __VERSION_H__
#define __VERSION_H__
-#define PPCBOOT_VERSION "PPCBoot 0.9.3-pre2"
+#define PPCBOOT_VERSION "PPCBoot 0.9.3-pre3"
#endif /* __VERSION_H__ */
projects / users / rw / ppcboot.git / commitdiff