Some SCIF devices specify the same IRQ. We can use SCIx_IRQ_MUXED for this.
And change use to evt2irq(), without specifying the value of IRQ directly.
This is correction to the SH4A series.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 80, 80, 80, 80 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xC00)),
 };
 
 static struct platform_device scif0_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 81, 81, 81, 81 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xC20)),
 };
 
 static struct platform_device scif1_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 82, 82, 82, 82 },
+       .irq            = SCIx_IRQ_MUXED(evt2irq(0xC40)),
 };
 
 static struct platform_device scif2_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 83, 83, 83, 83 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xC60)),
 };
 
 static struct platform_device scif3_device = {
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 80, 80, 80, 80 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xC00)),
 };
 
 static struct platform_device scif0_device = {
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 80, 80, 80, 80 },
+       .irqs                   = SCIx_IRQ_MUXED(evt2irq(0xC00)),
        .ops            = &sh7722_sci_port_ops,
        .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 81, 81, 81, 81 },
+       .irqs                   = SCIx_IRQ_MUXED(evt2irq(0xC20)),
        .ops            = &sh7722_sci_port_ops,
        .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 82, 82, 82, 82 },
+       .irqs                   = SCIx_IRQ_MUXED(evt2irq(0xC40)),
        .ops            = &sh7722_sci_port_ops,
        .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 80, 80, 80, 80 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xC00)),
        .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 81, 81, 81, 81 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xC20)),
        .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 82, 82, 82, 82 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xC40)),
        .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 80, 80, 80, 80 },
+       .irqs                   = SCIx_IRQ_MUXED(evt2irq(0xC00)),
        .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 81, 81, 81, 81 },
+       .irqs                   = SCIx_IRQ_MUXED(evt2irq(0xC20)),
        .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 82, 82, 82, 82 },
+       .irqs                   = SCIx_IRQ_MUXED(evt2irq(0xC40)),
        .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_3,
        .type           = PORT_SCIFA,
-       .irqs           = { 56, 56, 56, 56 },
+       .irqs                   = SCIx_IRQ_MUXED(evt2irq(0x900)),
 };
 
 static struct platform_device scif3_device = {
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_3,
        .type           = PORT_SCIFA,
-       .irqs           = { 88, 88, 88, 88 },
+       .irqs                   = SCIx_IRQ_MUXED(evt2irq(0xD00)),
 };
 
 static struct platform_device scif4_device = {
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_3,
        .type           = PORT_SCIFA,
-       .irqs           = { 109, 109, 109, 109 },
+       .irqs                   = SCIx_IRQ_MUXED(evt2irq(0xFA0)),
 };
 
 static struct platform_device scif5_device = {
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 40, 40, 40, 40 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
 };
 
 static struct platform_device scif2_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 76, 76, 76, 76 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xB80)),
 };
 
 static struct platform_device scif3_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 104, 104, 104, 104 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xF00)),
 };
 
 static struct platform_device scif4_device = {
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 40, 40, 40, 40 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 76, 76, 76, 76 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xB80)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 104, 104, 104, 104 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xF00)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 61, 61, 61, 61 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9A0)),
 };
 
 static struct platform_device scif0_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 62, 62, 62, 62 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9C0)),
 };
 
 static struct platform_device scif1_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 63, 63, 63, 63 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9E0)),
 };
 
 static struct platform_device scif2_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 64, 64, 64, 64 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xA00)),
 };
 
 static struct platform_device scif3_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 65, 65, 65, 65 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xA20)),
 };
 
 static struct platform_device scif4_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 66, 66, 66, 66 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xA40)),
 };
 
 static struct platform_device scif5_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 67, 67, 67, 67 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xA60)),
 };
 
 static struct platform_device scif6_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 68, 68, 68, 68 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xA80)),
 };
 
 static struct platform_device scif7_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 69, 69, 69, 69 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xAA0)),
 };
 
 static struct platform_device scif8_device = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-       .irqs           = { 70, 70, 70, 70 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0xAC0)),
 };
 
 static struct platform_device scif9_device = {
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 40, 40, 40, 40 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 44, 44, 44, 44 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x780)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 60, 60, 60, 60 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x980)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 61, 61, 61, 61 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9A0)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 62, 62, 62, 62 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9C0)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 63, 63, 63, 63 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9E0)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 44, 44, 44, 44 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x780)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 50, 50, 50, 50 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x840)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 51, 51, 51, 51 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x860)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 52, 52, 52, 52 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x880)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_1,
        .type           = PORT_SCIF,
-       .irqs           = { 53, 53, 53, 53 },
+       .irqs           = SCIx_IRQ_MUXED(evt2irq(0x8A0)),
        .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };