struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
 
-uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
-                             struct dma_fence *fence);
+int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
+                             struct dma_fence *fence, uint64_t *seq);
 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
                                   struct amdgpu_ring *ring, uint64_t seq);
 
 
        struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
        struct amdgpu_job *job;
        unsigned i;
+       uint64_t seq;
+
        int r;
 
        amdgpu_mn_lock(p->mn);
        job->fence_ctx = entity->fence_context;
        p->fence = dma_fence_get(&job->base.s_fence->finished);
 
+       r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
+       if (r) {
+               dma_fence_put(p->fence);
+               dma_fence_put(&job->base.s_fence->finished);
+               amdgpu_job_free(job);
+               amdgpu_mn_unlock(p->mn);
+               return r;
+       }
+
        amdgpu_cs_post_dependencies(p);
 
-       cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
-       job->uf_sequence = cs->out.handle;
+       cs->out.handle = seq;
+       job->uf_sequence = seq;
+
        amdgpu_job_free_resources(job);
 
        trace_amdgpu_cs_ioctl(job);
 
        return 0;
 }
 
-uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
-                             struct dma_fence *fence)
+int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
+                             struct dma_fence *fence, uint64_t* handler)
 {
        struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
        uint64_t seq = cring->sequence;
        other = cring->fences[idx];
        if (other) {
                signed long r;
-               r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
+               r = dma_fence_wait_timeout(other, true, MAX_SCHEDULE_TIMEOUT);
                if (r < 0)
-                       DRM_ERROR("Error (%ld) waiting for fence!\n", r);
+                       return r;
        }
 
        dma_fence_get(fence);
        spin_unlock(&ctx->ring_lock);
 
        dma_fence_put(other);
+       if (handler)
+               *handler = seq;
 
-       return seq;
+       return 0;
 }
 
 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,