Merge tag 'drm-intel-next-2021-12-14' of ssh://git.freedesktop.org/git/drm/drm-intel...

drm/i915 feature pull #2 for v5.17:

Features and functionality:
- Add eDP privacy screen support (Hans)
- Add Raptor Lake S (RPL-S) support (Anusha)
- Add CD clock squashing support (Mika)
- Properly support ADL-P without force probe (Clint)
- Enable pipe color support (10 bit gamma) for display 13 platforms (Uma)
- Update ADL-P DMC firmware to v2.14 (Madhumitha)

Refactoring and cleanups:
- More FBC refactoring preparing for multiple FBC instances (Ville)
- Plane register cleanups (Ville)
- Header refactoring and include cleanups (Jani)
- Crtc helper and vblank wait function cleanups (Jani, Ville)
- Move pipe/transcoder/abox masks under intel_device_info.display (Ville)

Fixes:
- Add a delay to let eDP source OUI write take effect (Lyude)
- Use div32 version of MPLLB word clock for UHBR on SNPS PHY (Jani)
- Fix DMC firmware loader overflow check (Harshit Mogalapalli)
- Fully disable FBC on FIFO underruns (Ville)
- Disable FBC with double wide pipe as mutually exclusive (Ville)
- DG2 workarounds (Matt)
- Non-x86 build fixes (Siva)
- Fix HDR plane max width for NV12 (Vidya)
- Disable IRQ for selftest timestamp calculation (Anshuman)
- ADL-P VBT DDC pin mapping fix (Tejas)

Merges:
- Backmerge drm-next for privacy screen plumbing (Jani)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87ee6f5h9u.fsf@intel.com

diff --cc drivers/gpu/drm/i915/Makefile
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_fbc.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_reset.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_driver.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
index d99e020773acd9ad4bcb52b73a0a01f20ca67988,e99996dfd43a121d8ba7e3758d18f27f3286ed8b..58aa55bc746114d4b932fc667721df28fd8fb657
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -1594,11 -1405,11 +1408,11 @@@ IS_SUBPLATFORM(const struct drm_i915_pr
   * and stepping-specific logic will be applied with a general DG2-wide stepping
   * number.
   */
 -#define IS_DG2_GT_STEP(__i915, variant, since, until) \
 +#define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
        (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
 -       IS_GT_STEP(__i915, since, until))
 +       IS_GRAPHICS_STEP(__i915, since, until))
  
- #define IS_DG2_DISP_STEP(__i915, since, until) \
+ #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
        (IS_DG2(__i915) && \
         IS_DISPLAY_STEP(__i915, since, until))
  

diff --cc drivers/gpu/drm/i915/i915_irq.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_pci.c
index f01cba4ec283dd6a677597571df22d0968761b6e,eeee028a5ad72789c86195d84182d170918a436e..ae36dfd77dcfa19be3d77fcbe1b002fd3493e126
--- 1/drivers/gpu/drm/i915/i915_pci.c
--- 2/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@@ -906,9 -904,9 +904,9 @@@ static const struct intel_device_info r
  static const struct intel_device_info dg1_info = {
        GEN12_FEATURES,
        DGFX_FEATURES,
 -      .graphics_rel = 10,
 +      .graphics.rel = 10,
        PLATFORM(INTEL_DG1),
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
        .require_force_probe = 1,
        .platform_engine_mask =
                BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |

diff --cc drivers/gpu/drm/i915/i915_reg.h
index 3450818802c26a5cd3fd9dc5d4a99f61e1c2ab3f,9e5ccf86088c046a51de0c757a8576d3dfdc158a..d27ba273cc687b6066d97de7271a4fb0f07d71dc
--- 1/drivers/gpu/drm/i915/i915_reg.h
--- 2/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -8573,13 -8484,10 +8574,14 @@@ enum 
                                                           _PIPEB_CHICKEN)
  #define   UNDERRUN_RECOVERY_DISABLE_ADLP      REG_BIT(30)
  #define   UNDERRUN_RECOVERY_ENABLE_DG2                REG_BIT(30)
- #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU    (1 << 15)
- #define   PER_PIXEL_ALPHA_BYPASS_EN           (1 << 7)
+ #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU    REG_BIT(15)
+ #define   DG2_RENDER_CCSTAG_4_3_EN            REG_BIT(12)
+ #define   PER_PIXEL_ALPHA_BYPASS_EN           REG_BIT(7)
  
 +#define VFLSKPD                               _MMIO(0x62a8)
 +#define   DIS_OVER_FETCH_CACHE                REG_BIT(1)
 +#define   DIS_MULT_MISS_RD_SQUASH     REG_BIT(0)
 +
  #define FF_MODE2                      _MMIO(0x6604)
  #define   FF_MODE2_GS_TIMER_MASK      REG_GENMASK(31, 24)
  #define   FF_MODE2_GS_TIMER_224               REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)

diff --cc drivers/gpu/drm/i915/intel_device_info.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_device_info.h
index 669f0d26c3c382ce4d4f2ec5d5c59cdb81b567dc,c121d7309dd23a8089ea4fae9e73fb7d2dd27d71..d9ac6540d058fe9f0d2f55deb021bf63ef1b07d7
--- 1/drivers/gpu/drm/i915/intel_device_info.h
--- 2/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@@ -203,8 -198,11 +201,12 @@@ struct intel_device_info 
  
        struct {
                u8 ver;
 +              u8 rel;
  
+               u8 pipe_mask;
+               u8 cpu_transcoder_mask;
+               u8 abox_mask;
+ 
  #define DEFINE_FLAG(name) u8 name:1
                DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
  #undef DEFINE_FLAG

diff --cc drivers/gpu/drm/i915/intel_pm.c
Simple merge