*/
        intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
        /* Clear interrupt */
-       if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
-                       EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
-                       cd->tx_check | cd->eesr_err_check)) {
+       if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) {
                sh_eth_write(ndev, intr_status, EESR);
                ret = IRQ_HANDLED;
        } else
                goto other_irq;
 
-       if (intr_status & (EESR_FRC | /* Frame recv*/
-                       EESR_RMAF | /* Multi cast address recv*/
-                       EESR_RRF  | /* Bit frame recv */
-                       EESR_RTLF | /* Long frame recv*/
-                       EESR_RTSF | /* short frame recv */
-                       EESR_PRE  | /* PHY-LSI recv error */
-                       EESR_CERF)){ /* recv frame CRC error */
+       if (intr_status & EESR_RX_CHECK)
                sh_eth_rx(ndev, intr_status);
-       }
 
        /* Tx Check */
        if (intr_status & cd->tx_check) {
 
        EESR_CERF       = 0x00000001,
 };
 
+#define EESR_RX_CHECK          (EESR_FRC  | /* Frame recv */           \
+                                EESR_RMAF | /* Multicast address recv */ \
+                                EESR_RRF  | /* Bit frame recv */       \
+                                EESR_RTLF | /* Long frame recv */      \
+                                EESR_RTSF | /* Short frame recv */     \
+                                EESR_PRE  | /* PHY-LSI recv error */   \
+                                EESR_CERF)  /* Recv frame CRC error */
+
 #define DEFAULT_TX_CHECK       (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
                                 EESR_RTO)
 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \