static const struct iwl_base_params iwl_a000_base_params = {
        .eeprom_size = OTP_LOW_IMAGE_SIZE_FAMILY_A000,
-       .num_of_queues = 31,
+       .num_of_queues = 512,
        .shadow_ram_support = true,
        .led_compensation = 57,
        .wd_timeout = IWL_LONG_WD_TIMEOUT,
 
           apmg_wake_up_wa:1,
           scd_chain_ext_wa:1;
 
-       u8 num_of_queues;       /* def: HW dependent */
+       u16 num_of_queues;      /* def: HW dependent */
 
        u8 max_ll_items;
        u8 led_compensation;
 
  * currently supports
  */
 #define IWL_MAX_HW_QUEUES              32
+#define IWL_MAX_TVQM_QUEUES            512
+
 #define IWL_MAX_TID_COUNT      8
 #define IWL_MGMT_TID           15
 #define IWL_FRAME_LIMIT        64
 
                u64 on_time_scan;
        } radio_stats, accu_radio_stats;
 
-       u8 hw_queue_to_mac80211[IWL_MAX_HW_QUEUES];
+       u8 hw_queue_to_mac80211[IWL_MAX_TVQM_QUEUES];
 
        struct {
                u8 hw_queue_refcount;
 
        struct iwl_dma_ptr kw;
 
        struct iwl_txq *txq_memory;
-       struct iwl_txq *txq[IWL_MAX_HW_QUEUES];
-       unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
-       unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
+       struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES];
+       unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
+       unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
 
        /* PCI bus related data */
        struct pci_dev *pci_dev;