Fixed PCU E configuration for other / bigger flash types.
* "last user address" is set even if bootp is used without parameters
(and it uses default address).
+======================================================================
+Modifications for 0.9.3:
+======================================================================
+
+* Completed support for CU824 board
+
+* Fixed PCU E configuration for other / bigger flash types
+
======================================================================
Modifications for 0.9.2:
======================================================================
ppcboot for a CU824 board
---------------------------
-The port is not complete yet. ppcboot for CU824 has been debugged to
-work okay when loaded into RAM using VxWorks Boot and run from RAM.
-Both serial consoles are operational as well as flash and ethernet
-drivers.
-
-In its current state, ppcboot for CU824 doesn't work from flash, even
-when burned into bank 1 of flash (not the one the processor jumps to
-on reset) and jumped to from VxWorks Boot or ppcboot started from RAM.
-
CU824 has two banks of flash 8MB each. In board's notation, bank 0 is
the one at the address of 0xFF800000 and bank 1 is the one at the
address of 0xFF000000. On power-up the processor jumps to the address
-of 0xFFF00100, the last megabyte of the bank 0 of flash.
-
-For debugging purposes, ppcboot for CU824 is set up to reside in the
-beginning of the bank 1 of flash, with the second parameter block of
-flash (the one at the address 0xFF008000) being devoted to store the
-environment. For the final version, in order to set up ppcboot for
-correct flash addresses (the last megabyte of the bank 0 of flash),
-appropriate changes should be made to the config_CU824.h and ppcboot.lds
-files to adjust the location of the environment.
-
-
-Things to do
-------------
-
-1. Make it work from the first bank of flash (at 0xFF000000).
-
-2. Reconfigure ppcboot to reside in the last megabyte of flash and
-debug the CPU-initialization code.
-
-
-Modifications made to common ppcboot files
-------------------------------------------
-
-Apart from CU824, ppcboot currently supports only one board with the
-MPC8240 processor, Sandpoint8240. The CPU-specific code appeared to
-have some inaccuracies, and efforts were made to correct them. Below
-is a list of modified files.
-
-cpu/mpc8240/config.mk
-
-Added the -mrelocatable compiler flag.
+of 0xFFF00100, the last megabyte of the bank 0 of flash. Thus,
+PPCBoot is configured to reside in flash starting at the address of
+0xFFF00000. The environment space is not embedded in the PPCBoot code
+and is located in flash separately from PPCBoot, at the address of
+0xFF008000.
-cpu/mpc8240/cpu.c
-Time-base clock variable is initialized to the CONFIG_SYS_CLK_FREQ
-constant now. The (idata->cpu_clk + 3L) / 4L expression appeared to
-be incorrect.
-
-cpu/mpc8240/cpu_init.c
-
-Fixed several typos and mistakes in parentheses. Also, MSARx and
-EMSARx registers were initialized incorrectly; now fixed.
-
-cpu/mpc8240/start.S
-
-In the monitor-relocation code, the source address changed to
-CFG_MONITOR_BASE.
-
-include/mpc8240.h
-
-Fixed a typo and several mistakes in PCI-access macros. Definitions
-of two new constants added.
-
-Also, the size of network buffers defined in include/net.h was changed
-from 608 to 1536 which is the correct value for ethernet packets and
-is crucial for the ethernet driver to operate correctly.
-
-Most of the modifications are made on the CONFIG_CU824 conditional,
-not to break the Sandpoint8240 support, even though it is believed
-the modifications are "right" and should be made common for all
-8240-based boards.
-
-
-RAM-loaded ppcboot test results
--------------------------------
+PPCBoot test results
+--------------------
x.x Operation on all available serial consoles
x.x.x CONFIG_CONS_INDEX 1
- VxWorks System Boot
-
-
-Copyright 1984-1998 Wind River Systems, Inc.
-
-
-
-
-
-CPU: MicroSys CU824 - MPC8240
-Version: 5.4
-BSP version: 1.2/2
-Creation date: Aug 3 2000, 09:15:30
-
-
-
-
-Press any key to stop auto-boot...
- 5
-
-[VxWorks Boot]: l
-
-boot device : dc
-unit number : 0
-processor number : 0
-host name : sky
-file name : /s/boot/nick/ppcboot
-inet on ethernet (e) : 172.16.1.57
-host inet (h) : 172.16.1.2
-flags (f) : 0x80
-target name (tn) : n00
-
-Attached TCP/IP interface to dc0.
-Attaching network interface lo0... done.
-Loading... 132072
-entry = 0x100000
-[VxWorks Boot]: g 100100
-Starting at 0x100100...
-
-
-
-ppcboot 0.8.3 (Apr 21 2001 - 18:05:08)
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
Initializing...
CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
Board: CU824 Revision 1 Local Bus at 99 MHz
DRAM: 64 MB
FLASH: 16 MB
-*** Warning - bad CRC, using default environment
-
In: serial
Out: serial
Err: serial
Hit any key to stop autoboot: 0
=>
-=>
-=>
-
-x.x.x CONFIG_CONS_INDEX 2
-
- VxWorks System Boot
-
-
-Copyright 1984-1998 Wind River Systems, Inc.
-
-
-
-
-
-CPU: MicroSys CU824 - MPC8240
-Version: 5.4
-BSP version: 1.2/2
-Creation date: Aug 3 2000, 09:15:30
-
-
-
-
-Press any key to stop auto-boot...
- 2
-
-[VxWorks Boot]: l
-
-boot device : dc
-unit number : 0
-processor number : 0
-host name : sky
-file name : /s/boot/nick/ppcboot
-inet on ethernet (e) : 172.16.1.57
-host inet (h) : 172.16.1.2
-flags (f) : 0x80
-target name (tn) : n00
-
-Attached TCP/IP interface to dc0.
-Attaching network interface lo0... done.
-Loading... 148456
-entry = 0x100000
-[VxWorks Boot]: g 100100
-Starting at 0x100100...
-
-..............
-Console cable reinserted into the socket 2
-..............
-
-=>
-=>
-=>
=>he
go - start application at address 'addr'
run - run commands in an environment variable
? - alias for 'help'
=>
-x.x Flash Driver Operation
-
-x.x.x Information
-
- VxWorks System Boot
-
-
-Copyright 1984-1998 Wind River Systems, Inc.
+x.x.x CONFIG_CONS_INDEX 2
+**** NOT TESTED ****
+x.x Flash Driver Operation
+x.x.x Erase Operation
-CPU: MicroSys CU824 - MPC8240
-Version: 5.4
-BSP version: 1.2/2
-Creation date: Aug 3 2000, 09:15:30
-
-
-
-
-Press any key to stop auto-boot...
- 5
-[VxWorks Boot]: l
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
-boot device : dc
-unit number : 0
-processor number : 0
-host name : sky
-file name : /s/boot/nick/ppcboot
-inet on ethernet (e) : 172.16.1.57
-host inet (h) : 172.16.1.2
-flags (f) : 0x80
-target name (tn) : n00
+Initializing...
+ CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+ Board: CU824 Revision 1 Local Bus at 99 MHz
+ DRAM: 64 MB
+ FLASH: 16 MB
+ In: serial
+ Out: serial
+ Err: serial
-Attached TCP/IP interface to dc0.
-Attaching network interface lo0... done.
-Loading... 148456
-entry = 0x100000
-[VxWorks Boot]: g 100100
-Starting at 0x100100...
+Hit any key to stop autoboot: 0
+=>
+=>
+=>
+=>md ff000000
+ff000000: 27051956 70706362 6f6f7420 302e382e '..Vppcboot 0.8.
+ff000010: 3320284d 61792031 31203230 3031202d 3 (May 11 2001 -
+ff000020: 2031343a 35373a30 33290000 00000000 14:57:03)......
+ff000030: 00000000 00000000 00000000 00000000 ................
+ff000040: 00000000 00000000 00000000 00000000 ................
+ff000050: 00000000 00000000 00000000 00000000 ................
+ff000060: 00000000 00000000 00000000 00000000 ................
+ff000070: 00000000 00000000 00000000 00000000 ................
+ff000080: 00000000 00000000 00000000 00000000 ................
+ff000090: 00000000 00000000 00000000 00000000 ................
+ff0000a0: 00000000 00000000 00000000 00000000 ................
+ff0000b0: 00000000 00000000 00000000 00000000 ................
+ff0000c0: 00000000 00000000 00000000 00000000 ................
+ff0000d0: 00000000 00000000 00000000 00000000 ................
+ff0000e0: 00000000 00000000 00000000 00000000 ................
+ff0000f0: 00000000 00000000 00000000 00000000 ................
+=>erase ff000000 ff007fff
+Erase Flash from 0xff000000 to 0xff007fff
+ done
+Erased 1 sectors
+=>md ff000000
+ff000000: ffffffff ffffffff ffffffff ffffffff ................
+ff000010: ffffffff ffffffff ffffffff ffffffff ................
+ff000020: ffffffff ffffffff ffffffff ffffffff ................
+ff000030: ffffffff ffffffff ffffffff ffffffff ................
+ff000040: ffffffff ffffffff ffffffff ffffffff ................
+ff000050: ffffffff ffffffff ffffffff ffffffff ................
+ff000060: ffffffff ffffffff ffffffff ffffffff ................
+ff000070: ffffffff ffffffff ffffffff ffffffff ................
+ff000080: ffffffff ffffffff ffffffff ffffffff ................
+ff000090: ffffffff ffffffff ffffffff ffffffff ................
+ff0000a0: ffffffff ffffffff ffffffff ffffffff ................
+ff0000b0: ffffffff ffffffff ffffffff ffffffff ................
+ff0000c0: ffffffff ffffffff ffffffff ffffffff ................
+ff0000d0: ffffffff ffffffff ffffffff ffffffff ................
+ff0000e0: ffffffff ffffffff ffffffff ffffffff ................
+ff0000f0: ffffffff ffffffff ffffffff ffffffff ................
+=>
+x.x.x Information
-ppcboot 0.8.3 (Apr 21 2001 - 18:05:08)
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
Initializing...
CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
Board: CU824 Revision 1 Local Bus at 99 MHz
DRAM: 64 MB
FLASH: 16 MB
-*** Warning - bad CRC, using default environment
-
In: serial
Out: serial
Err: serial
Hit any key to stop autoboot: 0
=>
=>
+=>
+=>
=>flinfo
-
+
Bank # 1: Intel: 28F160F3B (16Mbit)
Size: 8 MB in 39 Sectors
Sector Start Addresses:
FF480000 FF4C0000 FF500000 FF540000 FF580000
FF5C0000 FF600000 FF640000 FF680000 FF6C0000
FF700000 FF740000 FF780000 FF7C0000
-
+
Bank # 2: Intel: 28F160F3B (16Mbit)
Size: 8 MB in 39 Sectors
Sector Start Addresses:
FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
- FFF00000 FFF40000 FFF80000 FFFC0000
+ FFF00000 (RO) FFF40000 FFF80000 FFFC0000
=>
-=>flinfo 2
+x.x.x Flash Programming
-Bank # 2: Intel: 28F160F3B (16Mbit)
- Size: 8 MB in 39 Sectors
- Sector Start Addresses:
- FF800000 FF808000 FF810000 FF818000 FF820000
- FF828000 FF830000 FF838000 FF840000 FF880000
- FF8C0000 FF900000 FF940000 FF980000 FF9C0000
- FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
- FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
- FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
- FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
- FFF00000 FFF40000 FFF80000 FFFC0000
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+ CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+ Board: CU824 Revision 1 Local Bus at 99 MHz
+ DRAM: 64 MB
+ FLASH: 16 MB
+ In: serial
+ Out: serial
+ Err: serial
+
+Hit any key to stop autoboot: 0
+=>
+=>
+=>
+=>
+=>cp 0 ff000000 20
+Copy to Flash... done
+=>md 0
+00000000: 0ec08ce0 03f9800c 00000001 040c0000 ................
+00000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................
+00000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4.
+00000030: 03fcd5bc 03fcdabc 00000000 00000000 ................
+00000040: 00000000 00000000 00000000 00000000 ................
+00000050: 00000000 00000000 00000000 00000000 ................
+00000060: 00000000 00000000 00000000 00000000 ................
+00000070: 00000000 00000000 00000000 00000000 ................
+00000080: 00000000 00000000 00000000 00000000 ................
+00000090: 00000000 00000000 00000000 00000000 ................
+000000a0: 00000000 00000000 00000000 00000000 ................
+000000b0: 00000000 00000000 00000000 00000000 ................
+000000c0: 00000000 00000000 00000000 00000000 ................
+000000d0: 00000000 00000000 00000000 00000000 ................
+000000e0: 00000000 00000000 00000000 00000000 ................
+000000f0: 00000000 00000000 00000000 00000000 ................
+=>md ff000000
+ff000000: 0ec08ce0 03f9800c 00000001 040c0000 ................
+ff000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................
+ff000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4.
+ff000030: 03fcd5bc 03fcdabc 00000000 00000000 ................
+ff000040: 00000000 00000000 00000000 00000000 ................
+ff000050: 00000000 00000000 00000000 00000000 ................
+ff000060: 00000000 00000000 00000000 00000000 ................
+ff000070: 00000000 00000000 00000000 00000000 ................
+ff000080: ffffffff ffffffff ffffffff ffffffff ................
+ff000090: ffffffff ffffffff ffffffff ffffffff ................
+ff0000a0: ffffffff ffffffff ffffffff ffffffff ................
+ff0000b0: ffffffff ffffffff ffffffff ffffffff ................
+ff0000c0: ffffffff ffffffff ffffffff ffffffff ................
+ff0000d0: ffffffff ffffffff ffffffff ffffffff ................
+ff0000e0: ffffffff ffffffff ffffffff ffffffff ................
+ff0000f0: ffffffff ffffffff ffffffff ffffffff ................
+=>
+
+x.x.x Storage of environment variables in flash
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+ CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+ Board: CU824 Revision 1 Local Bus at 99 MHz
+ DRAM: 64 MB
+ FLASH: 16 MB
+ In: serial
+ Out: serial
+ Err: serial
+
+Hit any key to stop autoboot: 0
+=>
+=>printenv
+bootargs=
+bootcmd=bootm FE020000
+bootdelay=5
+baudrate=9600
+ipaddr=192.168.4.2
+serverip=192.168.4.1
+ethaddr=00:40:42:01:00:a0
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 167/32764 bytes
+=>setenv myvar 1234
+=>save_env
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Saving Environment to Flash...
+Protected 1 sectors
+=>reset
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+ CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+ Board: CU824 Revision 1 Local Bus at 99 MHz
+ DRAM: 64 MB
+ FLASH: 16 MB
+ In: serial
+ Out: serial
+ Err: serial
+
+Hit any key to stop autoboot: 0
+=>
+=>printenv
+bootargs=
+bootcmd=bootm FE020000
+bootdelay=5
+baudrate=9600
+ipaddr=192.168.4.2
+serverip=192.168.4.1
+ethaddr=00:40:42:01:00:a0
+myvar=1234
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 178/32764 bytes
=>
x.x Image Download and run over serial port
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+ CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+ Board: CU824 Revision 1 Local Bus at 99 MHz
+ DRAM: 64 MB
+ FLASH: 16 MB
+ In: serial
+ Out: serial
+ Err: serial
+
+Hit any key to stop autoboot: 0
+=>
+=>
=>mw 40000 0 10000
=>md 40000
00040000: 00000000 00000000 00000000 00000000 ................
=>loads
## Ready for S-Record download ...
-(Back at iron)
-[nick@iron nick]$ cat ppcboot-0.8.3.cu824/examples/hello_world
-hello_world hello_world.c hello_world.srec
-[nick@iron nick]$ cat ppcboot-0.8.3.cu824/examples/hello_world.srec >/dev/ttyS0
-[nick@iron nick]$ kermit -l /dev/ttyS0 -b 9600 -c
-Warning: terminal type unknown: "xterm"
-Fullscreen file transfer display disabled.
+(Back at xpert.denx.de)
+[vlad@xpert vlad]$ cat hello_world.srec >/dev/ttyS0
+[vlad@xpert vlad]$ kermit -l /dev/ttyS0 -b 9600 -c
Connecting to /dev/ttyS0, speed 9600.
The escape character is Ctrl-\ (ASCII 28, FS)
Type the escape character followed by C to get back,
argv[0] = "40004"
argv[1] = "<NULL>"
Hit any key to exit ...
-
+
## Application terminated, rc = 0x0
=>
x.x Image download and run over ethernet interface
-..... On the host......
-
-[nick@iron ppcboot-0.8.3.cu824]$ /opt/hardhat/devkit/ppc/82xx/bin/ppc_82xx-objcopy -O binary examples/hello_world /s/boot/sm.tmp
-[nick@iron ppcboot-0.8.3.cu824]$
-
-..... On the target .....
-
- VxWorks System Boot
-
-
-Copyright 1984-1998 Wind River Systems, Inc.
-
-
-
-
-
-CPU: MicroSys CU824 - MPC8240
-Version: 5.4
-BSP version: 1.2/2
-Creation date: Aug 3 2000, 09:15:30
-
-
-
-
-Press any key to stop auto-boot...
- 6
-
-[VxWorks Boot]: l
-
-boot device : dc
-unit number : 0
-processor number : 0
-host name : sky
-file name : /s/boot/nick/ppcboot
-inet on ethernet (e) : 172.16.1.57
-host inet (h) : 172.16.1.2
-flags (f) : 0x80
-target name (tn) : n00
-
-Attached TCP/IP interface to dc0.
-Attaching network interface lo0... done.
-Loading... 148456
-entry = 0x100000
-[VxWorks Boot]: g 100100
-Starting at 0x100100...
-
-
-
-ppcboot 0.8.3 (Apr 21 2001 - 18:05:08)
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
Initializing...
CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
Board: CU824 Revision 1 Local Bus at 99 MHz
DRAM: 64 MB
FLASH: 16 MB
-*** Warning - bad CRC, using default environment
-
In: serial
Out: serial
Err: serial
-
+
Hit any key to stop autoboot: 0
-=>setenv ethaddr 66:55:44:33:22:11
+=>
+=>
=>mw 40000 0 10000
=>md 40000
00040000: 00000000 00000000 00000000 00000000 ................
000400d0: 00000000 00000000 00000000 00000000 ................
000400e0: 00000000 00000000 00000000 00000000 ................
000400f0: 00000000 00000000 00000000 00000000 ................
-=>bootp 40000
-BOOTP broadcast 1
+=>tftpboot 40000 hello_world.bin
ARP broadcast 1
-TFTP from server 172.16.1.2; our IP address is 172.16.1.57
-Filename '/s/boot/sm.tmp'.
+TFTP from server 192.168.4.1; our IP address is 192.168.4.2
+Filename 'hello_world.bin'.
Load address: 0x40000
Loading: #############
done
argv[0] = "40004"
argv[1] = "<NULL>"
Hit any key to exit ...
-
+
## Application terminated, rc = 0x0
=>
-
#
#
-# Sandpoint boards
+# CU824 board
#
-TEXT_BASE = 0xFF000000
+TEXT_BASE = 0xFFF00000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
#define BOARD_REV_REG 0xFE80002B
+ /* We have to clear the initial data area here. Couldn't have done it
+ * earlier because DRAM had not been initialized.
+ */
+int board_pre_init(void)
+{
+ memset((void *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET),
+ 0,
+ CFG_INIT_DATA_SIZE);
+
+ return 0;
+}
+
int checkboard(void)
{
char revision = *(volatile char *)(BOARD_REV_REG);
long int initdram(int board_type)
{
-#if 0
- int val;
-
- printf("\n");
-#if 1
- CONFIG_READ_HALFWORD(PCICR, val);
- printf("PCICR = 0x%04X\n", val);
- CONFIG_READ_WORD(PICR1, val);
- printf("PICR1 = 0x%08X\n", val);
- CONFIG_READ_HALFWORD(PCISR, val);
- printf("PCISR = 0x%04X\n", val);
- CONFIG_READ_WORD(PICR2, val);
- printf("PICR2 = 0x%08X\n", val);
- CONFIG_READ_WORD(EUMBBAR, val);
- printf("EMUMBAR = 0x%08X\n", val);
- CONFIG_READ_WORD(MCCR1, val);
- printf("MCCR1 = 0x%08X\n", val);
- CONFIG_READ_WORD(MCCR2, val);
- printf("MCCR2 = 0x%08X\n", val);
- CONFIG_READ_WORD(MCCR3, val);
- printf("MCCR3 = 0x%08X\n", val);
- CONFIG_READ_WORD(MCCR4, val);
- printf("MCCR4 = 0x%08X\n", val);
- CONFIG_READ_WORD(MSAR1, val);
- printf("MSAR1 = 0x%08X\n", val);
- CONFIG_READ_WORD(EMSAR1, val);
- printf("EMSAR1 = 0x%08X\n", val);
- CONFIG_READ_WORD(MSAR2, val);
- printf("MSAR2 = 0x%08X\n", val);
- CONFIG_READ_WORD(EMSAR2, val);
- printf("EMSAR2 = 0x%08X\n", val);
- CONFIG_READ_WORD(MEAR1, val);
- printf("MEAR1 = 0x%08X\n", val);
- CONFIG_READ_WORD(EMEAR1, val);
- printf("EMEAR1 = 0x%08X\n", val);
- CONFIG_READ_WORD(MEAR2, val);
- printf("MEAR2 = 0x%08X\n", val);
- CONFIG_READ_WORD(EMEAR2, val);
- printf("EMEAR2 = 0x%08X\n", val);
- CONFIG_READ_BYTE(ODCR, val);
- printf("ORCR = 0x%02X\n", val);
- CONFIG_READ_BYTE(MBER, val);
- printf("MBER = 0x%02X\n", val);
-#endif
- CONFIG_READ_WORD(MCCR1, val);
- CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); //set memory access going
- __asm__ __volatile__("eieio");
- CONFIG_READ_WORD(MCCR1, val);
- printf("MCCR1 = 0x%08X\n", val);
-
- printf("IBAT0L = 0x%08X\n", mfspr(IBAT0L));
- printf("IBAT0U = 0x%08X\n", mfspr(IBAT0U));
- printf("IBAT1L = 0x%08X\n", mfspr(IBAT1L));
- printf("IBAT1U = 0x%08X\n", mfspr(IBAT1U));
- printf("IBAT2L = 0x%08X\n", mfspr(IBAT2L));
- printf("IBAT2U = 0x%08X\n", mfspr(IBAT2U));
- printf("IBAT3L = 0x%08X\n", mfspr(IBAT3L));
- printf("IBAT3U = 0x%08X\n", mfspr(IBAT3U));
- printf("DBAT0L = 0x%08X\n", mfspr(DBAT0L));
- printf("DBAT0U = 0x%08X\n", mfspr(DBAT0U));
- printf("DBAT1L = 0x%08X\n", mfspr(DBAT1L));
- printf("DBAT1U = 0x%08X\n", mfspr(DBAT1U));
- printf("DBAT2L = 0x%08X\n", mfspr(DBAT2L));
- printf("DBAT2U = 0x%08X\n", mfspr(DBAT2U));
- printf("DBAT3L = 0x%08X\n", mfspr(DBAT3L));
- printf("DBAT3U = 0x%08X\n", mfspr(DBAT3U));
-
- printf("huy = 0x%08X\n", (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) |
- (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT));
- printf("huy = 0x%08X\n", (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) |
- (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO);
-#endif
-
+ /* Nothing left to init here. Everthing is done in cpu_init_f().
+ */
return CFG_RAM_SIZE;
}
#define DE4X5_STS iobase + 0x028 /* Status Register */
#define DE4X5_OMR iobase + 0x030 /* Operation Mode Register */
#define DE4X5_SICR iobase + 0x068 /* SIA Connectivity Register */
-
+#define DE4X5_APROM iobase + 0x048 /* Ethernet Address PROM */
/* Register bits.
*/
#define STS_RS 0x000e0000 /* Receive Process State */
#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
#define OMR_SR 0x00000002 /* Start/Stop Receive */
-
+#define OMR_PS 0x00040000 /* Port Select */
+#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
+#define OMR_PM 0x00000080 /* Pass All Multicast */
/* Descriptor bits.
*/
#define R_OWN 0x80000000 /* Own Bit */
#define RD_RER 0x02000000 /* Receive End Of Ring */
+#define RD_LS 0x00000100 /* Last Descriptor */
+#define RD_ES 0x00008000 /* Error Summary */
#define TD_TER 0x02000000 /* Transmit End Of Ring */
#define T_OWN 0x80000000 /* Own Bit */
#define TD_LS 0x40000000 /* Last Segment */
#define TD_FS 0x20000000 /* First Segment */
-#define R_OWN 0x80000000 /* Own Bit */
-#define RD_LS 0x00000100 /* Last Descriptor */
-#define RD_ES 0x00008000 /* Error Summary */
+#define TD_ES 0x00008000 /* Error Summary */
+#define TD_SET 0x08000000 /* Setup Packet */
+
+
+#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
+#define SROM_RD 0x00004000 /* Read from Boot ROM */
+#define SROM_SR 0x00000800 /* Select Serial ROM when set */
+
+#define DT_IN 0x00000004 /* Serial Data In */
+#define DT_CLK 0x00000002 /* Serial ROM Clock */
+#define DT_CS 0x00000001 /* Serial ROM Chip Select */
#define POLL_DEMAND 1
#define NUM_RX_DESC PKTBUFSRX
#define NUM_TX_DESC 1 /* Number of TX descriptors */
-#define RX_BUFF_SZ PKTSIZE
+#define RX_BUFF_SZ PKTSIZE_ALIGN
#define TOUT_LOOP 1000000
+#define SETUP_FRAME_LEN 192
+#define ETH_ALEN 6
+
+
struct de4x5_desc {
volatile s32 status;
u32 des1;
static u_long iobase;
+static void send_setup_frame(bd_t * bis);
+static void check_hw_addr(bd_t * bis);
+static short srom_rd(u_long address, u_char offset);
+static void srom_latch(u_int command, u_long address);
+static void srom_command(u_int command, u_long address);
+static void srom_address(u_int command, u_long address, u_char offset);
+static short srom_data(u_int command, u_long address);
+static void sendto_srom(u_int command, u_long addr);
+static int getfrom_srom(u_long addr);
+
static inline int inl(u_long addr)
{
return le32_to_cpu(*(volatile u_long *)(addr + 0xfe000000));
udelay(10 * 1000);
+ check_hw_addr(bis);
+
RESET_DE4X5;
if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0)
printf("Error: Can not reset ethernet controller.\n");
goto Done;
}
+
+ outl(OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
for (i = 0; i < NUM_RX_DESC; i++)
{
tx_new = 0;
rx_new = 0;
+ send_setup_frame(bis);
+
Done:
return 0;
}
tx_ring[tx_new].buf = cpu_to_le32((u_long)packet);
- tx_ring[tx_new].des1 |= cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
+ tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
tx_ring[tx_new].status = cpu_to_le32(T_OWN);
outl(POLL_DEMAND, DE4X5_TPD);
}
}
+ if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES)
+ {
+ printf("TX error status = 0x%08X\n",
+ le32_to_cpu(tx_ring[tx_new].status));
+ status++;
+ }
+
out:
return status;
}
CONFIG_WRITE_BYTE(0x80000000 | CFG_ETH_DEV_FN | PCI_CFDA_PSM, SLEEP);
}
+static void check_hw_addr(bd_t *bis)
+{
+ unsigned char hw_addr[ETH_ALEN];
+ u_short tmp, *p = (short *)(&hw_addr[0]);
+ int i, j = 0;
+
+ for (i = 0; i < (ETH_ALEN >> 1); i++)
+ {
+ tmp = srom_rd(DE4X5_APROM, (SROM_HWADD >> 1) + i);
+ *p = le16_to_cpu(tmp);
+ j += *p++;
+ }
+
+ if ((j == 0) || (j == 0x2fffd))
+ {
+ printf("Warning: can't read HW address from SROM.\n");
+ goto Done;
+ }
+
+ for (i = 0; i < ETH_ALEN; i++)
+ {
+ if (hw_addr[i] != bis->bi_enetaddr[i])
+ {
+ printf("Warning: HW addresses don't match:\n");
+ printf("Address in SROM is "
+ "%02X:%02X:%02X:%02X:%02X:%02X\n",
+ hw_addr[0], hw_addr[1], hw_addr[2],
+ hw_addr[3], hw_addr[4], hw_addr[5]);
+ printf("Address used by ppcboot is "
+ "%02X:%02X:%02X:%02X:%02X:%02X\n",
+ bis->bi_enetaddr[0], bis->bi_enetaddr[1],
+ bis->bi_enetaddr[2], bis->bi_enetaddr[3],
+ bis->bi_enetaddr[4], bis->bi_enetaddr[5]);
+ goto Done;
+ }
+ }
+
+ Done:
+}
+
+static void send_setup_frame(bd_t *bis)
+{
+ int i;
+ char setup_frame[SETUP_FRAME_LEN];
+ char * pa = &setup_frame[0];
+
+ memset(pa, 0xff, SETUP_FRAME_LEN);
+
+ for (i = 0; i < ETH_ALEN; i++)
+ {
+ *(pa + (i & 1)) = bis->bi_enetaddr[i];
+ if (i & 0x01)
+ {
+ pa += 4;
+ }
+ }
+
+ for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++)
+ {
+ if (i >= TOUT_LOOP)
+ {
+ printf("eth: tx error buffer not ready\n");
+ goto out;
+ }
+ }
+
+ tx_ring[tx_new].buf = cpu_to_le32((u_long)&setup_frame[0]);
+ tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
+ tx_ring[tx_new].status = cpu_to_le32(T_OWN);
+
+ outl(POLL_DEMAND, DE4X5_TPD);
+
+ for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++)
+ {
+ if (i >= TOUT_LOOP)
+ {
+ printf("eth: tx buffer not ready\n");
+ goto out;
+ }
+ }
+
+ if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF)
+ {
+ printf("TX error status = 0x%08X\n",
+ le32_to_cpu(tx_ring[tx_new].status));
+ }
+ out:
+}
+
+ /* SROM Read.
+ */
+static short
+srom_rd(u_long addr, u_char offset)
+{
+ sendto_srom(SROM_RD | SROM_SR, addr);
+
+ srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
+ srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
+ srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
+
+ return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
+}
+
+static void
+srom_latch(u_int command, u_long addr)
+{
+ sendto_srom(command, addr);
+ sendto_srom(command | DT_CLK, addr);
+ sendto_srom(command, addr);
+
+ return;
+}
+
+static void
+srom_command(u_int command, u_long addr)
+{
+ srom_latch(command, addr);
+ srom_latch(command, addr);
+ srom_latch((command & 0x0000ff00) | DT_CS, addr);
+
+ return;
+}
+
+static void
+srom_address(u_int command, u_long addr, u_char offset)
+{
+ int i;
+ signed char a;
+
+ a = (char)(offset << 2);
+ for (i=0; i<6; i++, a <<= 1) {
+ srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
+ }
+ udelay(1);
+
+ i = (getfrom_srom(addr) >> 3) & 0x01;
+
+ return;
+}
+
+static short
+srom_data(u_int command, u_long addr)
+{
+ int i;
+ short word = 0;
+ s32 tmp;
+
+ for (i=0; i<16; i++) {
+ sendto_srom(command | DT_CLK, addr);
+ tmp = getfrom_srom(addr);
+ sendto_srom(command, addr);
+
+ word = (word << 1) | ((tmp >> 3) & 0x01);
+ }
+
+ sendto_srom(command & 0x0000ff00, addr);
+
+ return word;
+}
+
+static void
+sendto_srom(u_int command, u_long addr)
+{
+ outl(command, addr);
+ udelay(1);
+
+ return;
+}
+
+static int
+getfrom_srom(u_long addr)
+{
+ s32 tmp;
+
+ tmp = inl(addr);
+ udelay(1);
+
+ return tmp;
+}
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
{
- flash_info[i].flash_id = 0x008988F4;
+ *(volatile u_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE) =
+ 0x00900090;
+ if (*(volatile u_long *)(CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE) ==
+ *(volatile u_long *)(CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE + 4) &&
+ *(volatile u_long *)(CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE) ==
+ 0x00890089 &&
+ *(volatile u_long *)(CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE + 8) ==
+ *(volatile u_long *)(CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE + 12) &&
+ *(volatile u_long *)(CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE + 8) ==
+ 0x88f488f4)
+ {
+ flash_info[i].flash_id = 0x008988F4;
+ }
+ else
+ {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ goto Done;
+ }
+ *(volatile u_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE) =
+ 0xffffffff;
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
{
if (j <= 7)
{
- flash_info[i].start[j] = CFG_FLASH_BASE + i * FLASH_BANK_SIZE +
+ flash_info[i].start[j] = CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE +
j * PARAM_SECT_SIZE;
}
else
{
- flash_info[i].start[j] = CFG_FLASH_BASE + i * FLASH_BANK_SIZE +
- (j - 7) * MAIN_SECT_SIZE;
+ flash_info[i].start[j] = CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE +
+ (j - 7)*MAIN_SECT_SIZE;
}
}
size += flash_info[i].size;
/* Protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[1]);
+#else
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
&flash_info[0]);
#endif
+#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[1]);
+#else
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
+#endif
#endif
+ Done:
return size;
}
printf("28F160F3B (16Mbit)\n");
break;
default:
- printf ("Unknown Chip Type\n");
+ printf("Unknown Chip Type\n");
+ goto Done;
break;
}
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
+
+ Done:
}
/*-----------------------------------------------------------------------
vu_long *addr = (vu_long *)(info->start[sect]);
unsigned long status;
- /* Disable interrupts which might cause a timeout here */
+ /* Disable interrupts which might cause a timeout
+ * here.
+ */
flag = disable_interrupts();
*addr = 0x00500050; /* clear status register */
udelay (1000);
while (((status = *addr) & 0x00800080) != 0x00800080) {
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now=get_timer(start)) >
+ CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
- *addr = 0x00B000B0; /* suspend erase */
- *addr = 0x00FF00FF; /* reset to read mode */
+ *addr = 0x00B000B0; /* suspend erase */
+ *addr = 0x00FF00FF; /* to read mode */
return;
}
/* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
+ if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
return 4;
}
- wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
+ wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */
/*
* handle unaligned start bytes
typedef struct NS16550 *NS16550_t;
-const NS16550_t COM_PORTS[] = { (NS16550_t) (0xfe8000a0),
- (NS16550_t) (0xfe8000e0) };
+const NS16550_t COM_PORTS[] = { (NS16550_t) (0xfe800080),
+ (NS16550_t) (0xfe8000c0) };
volatile struct NS16550 *
NS16550_init(int chan, int baud_divisor)
ppc/crc32.o (.text)
ppc/zlib.o (.text)
- . = env_offset;
+ . = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
#include <ppcboot.h>
#include "ns16550.h"
-volatile struct NS16550 *console;
+#if CONFIG_CONS_INDEX == 1
+static struct NS16550 *console = 0xFE800080;
+#elif CONFIG_CONS_INDEX == 2
+static struct NS16550 *console = 0xFE8000C0;
+#else
+#error no valid console defined
+#endif
void
serial_init (unsigned long dummy, int baudrate)
{
int clock_divisor = CFG_SERIAL_CLOCK / 16 / baudrate;
- console = NS16550_init(CONFIG_CONS_INDEX - 1, clock_divisor);
+ NS16550_init(CONFIG_CONS_INDEX - 1, clock_divisor);
}
void
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
+ short n;
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- }
- while (base < info->size) { /* 64k regular sectors */
- info->start[i] = base;
- base += 64 << 10;
- ++i;
- }
- } else {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) {
+ return;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AMDL322T:
+ case FLASH_AMDL323T:
+ case FLASH_AMDL324T:
/* set sector offsets for top boot block type */
- short n;
base += info->size;
i = info->sector_count;
- for (n=0; n<8; ++n) {
+ for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
base -= 8 << 10;
--i;
info->start[i] = base;
}
- while (i > 0) {
+ while (i > 0) { /* 64k regular sectors */
base -= 64 << 10;
--i;
info->start[i] = base;
}
+ return;
+ case FLASH_AMDL322B:
+ case FLASH_AMDL323B:
+ case FLASH_AMDL324B:
+ /* set sector offsets for bottom boot block type */
+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ }
+ while (base < info->size) { /* 64k regular sectors */
+ info->start[i] = base;
+ base += 64 << 10;
+ ++i;
+ }
+ return;
+ case FLASH_AMDL640:
+ /* set sector offsets for dual boot block type */
+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ }
+ n = info->sector_count - 8;
+ while (i < n) { /* 64k regular sectors */
+ info->start[i] = base;
+ base += 64 << 10;
+ ++i;
+ }
+ while (i < info->sector_count) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ ++i;
+ }
+ return;
+ default:
+ return;
}
-
+ /* NOTREACHED */
}
/*-----------------------------------------------------------------------
break;
case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n");
break;
+ case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n");
+ break;
default: printf ("Unknown Chip Type 0x%lX\n",
info->flash_id);
break;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 8 MB */
+ case (AMD_ID_DL640 & 0xFFFF):
+ info->flash_id += FLASH_AMDL640;
+ info->sector_count = 142;
+ info->size = 0x00800000;
+ break;
default:
DEBUGF("Unknown Device ID\n");
info->flash_id = FLASH_UNKNOWN;
defined(CONFIG_CPCIISER4) || \
defined(CONFIG_ADCIOP) || \
defined(CONFIG_LWMON) || \
- defined(CONFIG_RPXSUPER)
+ defined(CONFIG_RPXSUPER) || \
+ defined(CONFIG_CU824)
board_pre_init(); /* very early board init code (fpga boot, etc.) */
#endif
#define CONFIG_MPC8240 1
#define CONFIG_CU824 1
-#define STOP_HERE __asm__ __volatile__ ( "trap" )
-#define CFG_RAMBOOT
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 9600
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
-#define CFG_MEMTEST_END 0x00100000 /* 0 ... 32 MB in DRAM */
+#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
/* Total amount of RAM.
*/
#define CFG_RAM_SIZE 0x04000000
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area
*/
*/
#define CFG_INIT_DATA_SIZE 128
-#define CFG_INIT_RAM_ADDR (CFG_RAM_SIZE - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_RAM_ADDR 0
#define CFG_INIT_DATA_OFFSET 0
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+ /* Warining: environment is not EMBEDDED in the ppcboot code.
+ * It's stored in flash separately.
+ */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */
+#define CFG_ENV_ADDR 0xFF008000
#define CFG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT 160 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
#if 1
-/* Start port with environment in flash; switch to EEPROM later */
+/* Start port with environment in flash; switch to SPI EEPROM later */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
#define CFG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
#define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */
#define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
+
#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
#define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */
#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */
#define FLASH_AMDL324B 0x0015
+#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */
+
#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */
#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
#define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */
: /* no output */ \
: "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
"r" (CONFIG_DATA), "r" (data), \
- "n" (3 - ((addr) & 3)));
+ "n" ((addr) & 3));
#define CONFIG_WRITE_HALFWORD( addr, data ) \
__asm__ ( \
sync " \
: "=r" (reg) \
: "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
- "r" (CONFIG_DATA), "n" ((3 - (addr)) & 3));
+ "r" (CONFIG_DATA), "n" ((addr) & 3));
#define CONFIG_READ_HALFWORD( addr , reg ) \
defined(CONFIG_CPCIISER4) || \
defined(CONFIG_ADCIOP) || \
defined(CONFIG_LWMON) || \
- defined(CONFIG_RPXSUPER)
+ defined(CONFIG_RPXSUPER) || \
+ defined(CONFIG_CU824)
/* $(BOARD)/$(BOARD).c */
int board_pre_init (void);
#endif
#ifndef __VERSION_H__
#define __VERSION_H__
-#define PPCBOOT_VERSION "ppcboot 0.9.2"
+#define PPCBOOT_VERSION "PPCBoot 0.9.3-pre1"
#endif /* __VERSION_H__ */
/* crc32.c -- compute the CRC-32 of a data stream
* Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
#include "zlib.h"
poly = 0L;
for (n = 0; n < sizeof(p)/sizeof(Byte); n++)
poly |= 1L << (31 - p[n]);
-
+
for (n = 0; n < 256; n++)
{
c = (uLong)n;
projects / users / rw / ppcboot.git / commitdiff