drm/i915/execlists: Flush the post-sync breadcrumb write harder

Quite rarely we see that the CS completion event fires before the
breadcrumb is coherent, which presumably is a result of the CS_STALL not
waiting for the post-sync operation. Try throwing in a DC_FLUSH into
the following pipecontrol to see if that makes any difference.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190827120615.31390-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a141e9e37bf7bb4026e370600ac9e62c35417885..171d5205962c00fd727456e41df98dddba173f97 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2923,8 +2923,10 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
                                      PIPE_CONTROL_DC_FLUSH_ENABLE);
 
        /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
+       /* XXX DC_FLUSH for post-sync write? (cf early context-switch bug) */
        cs = gen8_emit_pipe_control(cs,
                                    PIPE_CONTROL_FLUSH_ENABLE |
+                                   PIPE_CONTROL_DC_FLUSH_ENABLE |
                                    PIPE_CONTROL_CS_STALL,
                                    0);