arm64: dts: renesas: r9a07g043u: Add DU node

Add DU node to RZ/G2UL SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240822162320.5084-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 1b3db8df4bbc92ea18351a18ada6ce24b799439a..a3998e5928f7c9a287edb5a3708f20726456eeae 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -153,6 +153,31 @@
                resets = <&cpg R9A07G043_LCDC_RESET_N>;
        };
 
+       du: display@10890000 {
+               compatible = "renesas,r9a07g043u-du";
+               reg = <0 0x10890000 0 0x10000>;
+               interrupts = <SOC_PERIPHERAL_IRQ(152) IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
+                        <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
+                        <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
+               clock-names = "aclk", "pclk", "vclk";
+               power-domains = <&cpg>;
+               resets = <&cpg R9A07G043_LCDC_RESET_N>;
+               renesas,vsps = <&vspd 0>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               du_out_rgb: endpoint {
+                               };
+                       };
+               };
+       };
+
        irqc: interrupt-controller@110a0000 {
                compatible = "renesas,r9a07g043u-irqc",
                             "renesas,rzg2l-irqc";