return 144000;
 }
 
-/* Compute the max pixel clock for new configuration. Uses atomic state if
- * that's non-NULL, look at current state otherwise. */
+/* Compute the max pixel clock for new configuration. */
 static int intel_mode_max_pixclk(struct drm_device *dev,
                                 struct drm_atomic_state *state)
 {
                intel_state->min_pixclk[i] = pixclk;
        }
 
-       if (!intel_state->active_crtcs)
-               return 0;
-
        for_each_pipe(dev_priv, pipe)
                max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
 
                intel_state->min_pixclk[i] = pixel_rate;
        }
 
-       if (!intel_state->active_crtcs)
-               return 0;
-
        for_each_pipe(dev_priv, pipe)
                max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
 
 
                if (ret < 0)
                        return ret;
+
+               DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
+                             intel_state->cdclk, intel_state->dev_cdclk);
        } else
                to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;