Revert "drm/amdgpu: Use generic hdp flush function"

This reverts commit 18a878fd8aef0ec21648a3782f55a79790cd4073.

Revert this temporarily to make it easier to fix a regression
in the HDP handling.

Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
index 7fd8f09c28e664a7ad861fca33cd2eb4fb0559cb..b6cf801939aa58ffd11893d5be642ee4df622d22 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
@@ -22,7 +22,6 @@
  */
 #include "amdgpu.h"
 #include "amdgpu_ras.h"
-#include <uapi/linux/kfd_ioctl.h>
 
 int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
 {
@@ -47,23 +46,3 @@ int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
        /* hdp ras follows amdgpu_ras_block_late_init_default for late init */
        return 0;
 }
-
-void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,
-                             struct amdgpu_ring *ring)
-{
-       if (!ring || !ring->funcs->emit_wreg) {
-               WREG32((adev->rmmio_remap.reg_offset +
-                       KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
-                              2,
-                      0);
-               RREG32((adev->rmmio_remap.reg_offset +
-                       KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
-                      2);
-       } else {
-               amdgpu_ring_emit_wreg(ring,
-                                     (adev->rmmio_remap.reg_offset +
-                                      KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
-                                             2,
-                                     0);
-       }
-}
\ No newline at end of file

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
index 4cfd932b7e91edf8633939cb2f8d1af7e529329c..7b8a6152dc8d9edac9e932b420b01f778fbd0a6f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
@@ -44,6 +44,4 @@ struct amdgpu_hdp {
 };
 
 int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev);
-void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,
-                             struct amdgpu_ring *ring);
 #endif /* __AMDGPU_HDP_H__ */

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index e6c0d86d34865bc0ebf21a01c2474ff752f90f08..f1dc13b3ab38e6afd4d5352e3a831a3d5f1583d6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -36,6 +36,17 @@
 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK     0x00020000L
 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
 
+static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
+                               struct amdgpu_ring *ring)
+{
+       if (!ring || !ring->funcs->emit_wreg) {
+               WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+               RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
+       } else {
+               amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+       }
+}
+
 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
                                    struct amdgpu_ring *ring)
 {
@@ -169,7 +180,7 @@ struct amdgpu_hdp_ras hdp_v4_0_ras = {
 };
 
 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
-       .flush_hdp = amdgpu_hdp_generic_flush,
+       .flush_hdp = hdp_v4_0_flush_hdp,
        .invalidate_hdp = hdp_v4_0_invalidate_hdp,
        .update_clock_gating = hdp_v4_0_update_clock_gating,
        .get_clock_gating_state = hdp_v4_0_get_clockgating_state,

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
index 8bc001dc9f631a19b2485d5be498031ae76c2a95..43195c07974808f24d0696a7c9a5d4405770d34b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
@@ -27,6 +27,17 @@
 #include "hdp/hdp_5_0_0_sh_mask.h"
 #include <uapi/linux/kfd_ioctl.h>
 
+static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,
+                               struct amdgpu_ring *ring)
+{
+       if (!ring || !ring->funcs->emit_wreg) {
+               WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+               RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
+       } else {
+               amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+       }
+}
+
 static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,
                                    struct amdgpu_ring *ring)
 {
@@ -206,7 +217,7 @@ static void hdp_v5_0_init_registers(struct amdgpu_device *adev)
 }
 
 const struct amdgpu_hdp_funcs hdp_v5_0_funcs = {
-       .flush_hdp = amdgpu_hdp_generic_flush,
+       .flush_hdp = hdp_v5_0_flush_hdp,
        .invalidate_hdp = hdp_v5_0_invalidate_hdp,
        .update_clock_gating = hdp_v5_0_update_clock_gating,
        .get_clock_gating_state = hdp_v5_0_get_clockgating_state,

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
index ec20daf4272c5d5951cf41ac9ccd0b93fc93593e..a88d25a06c29b553bcadc0c9cbb9c2c43fc2301e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
@@ -30,6 +30,17 @@
 #define regHDP_CLK_CNTL_V6_1   0xd5
 #define regHDP_CLK_CNTL_V6_1_BASE_IDX 0
 
+static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
+                               struct amdgpu_ring *ring)
+{
+       if (!ring || !ring->funcs->emit_wreg) {
+               WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+               RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
+       } else {
+               amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+       }
+}
+
 static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
                                         bool enable)
 {
@@ -138,7 +149,7 @@ static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
 }
 
 const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
-       .flush_hdp = amdgpu_hdp_generic_flush,
+       .flush_hdp = hdp_v6_0_flush_hdp,
        .update_clock_gating = hdp_v6_0_update_clock_gating,
        .get_clock_gating_state = hdp_v6_0_get_clockgating_state,
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
index ed1debc035073a3f7348c1f21c2e89611d90516c..49f7eb4fbd117d1af6e5a252d26ded71283b13d0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
@@ -27,6 +27,17 @@
 #include "hdp/hdp_7_0_0_sh_mask.h"
 #include <uapi/linux/kfd_ioctl.h>
 
+static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev,
+                               struct amdgpu_ring *ring)
+{
+       if (!ring || !ring->funcs->emit_wreg) {
+               WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+               RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
+       } else {
+               amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+       }
+}
+
 static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev,
                                         bool enable)
 {
@@ -126,7 +137,7 @@ static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev,
 }
 
 const struct amdgpu_hdp_funcs hdp_v7_0_funcs = {
-       .flush_hdp = amdgpu_hdp_generic_flush,
+       .flush_hdp = hdp_v7_0_flush_hdp,
        .update_clock_gating = hdp_v7_0_update_clock_gating,
        .get_clock_gating_state = hdp_v7_0_get_clockgating_state,
 };