#include "dma.h"
 #include "soc.h"
 
+/*
+ * dma register field offset calculation
+ */
+#define DMA64REGOFFS(field)            offsetof(struct dma64regs, field)
+#define DMA64TXREGOFFS(di, field)      (di->d64txregbase + DMA64REGOFFS(field))
+#define DMA64RXREGOFFS(di, field)      (di->d64rxregbase + DMA64REGOFFS(field))
+
 /*
  * DMA hardware requires each descriptor ring to be 8kB aligned, and fit within
  * a contiguous 8kB physical address.
        bool addrext;   /* this dma engine supports DmaExtendedAddrChanges */
 
        /* 64-bit dma tx engine registers */
-       struct dma64regs __iomem *d64txregs;
+       uint d64txregbase;
        /* 64-bit dma rx engine registers */
-       struct dma64regs __iomem *d64rxregs;
+       uint d64rxregbase;
        /* pointer to dma64 tx descriptor ring */
        struct dma64desc *txd64;
        /* pointer to dma64 rx descriptor ring */
        if (dmactrlflags & DMA_CTRL_PEN) {
                u32 control;
 
-               control = R_REG(&di->d64txregs->control);
-               W_REG(&di->d64txregs->control,
+               control = bcma_read32(di->d11core, DMA64TXREGOFFS(di, control));
+               bcma_write32(di->d11core, DMA64TXREGOFFS(di, control),
                      control | D64_XC_PD);
-               if (R_REG(&di->d64txregs->control) & D64_XC_PD)
+               if (bcma_read32(di->d11core, DMA64TXREGOFFS(di, control)) &
+                   D64_XC_PD)
                        /* We *can* disable it so it is supported,
                         * restore control register
                         */
-                       W_REG(&di->d64txregs->control,
-                       control);
+                       bcma_write32(di->d11core, DMA64TXREGOFFS(di, control),
+                                    control);
                else
                        /* Not supported, don't allow it to be enabled */
                        dmactrlflags &= ~DMA_CTRL_PEN;
        return dmactrlflags;
 }
 
-static bool _dma64_addrext(struct dma64regs __iomem *dma64regs)
+static bool _dma64_addrext(struct dma_info *di, uint ctrl_offset)
 {
        u32 w;
-       OR_REG(&dma64regs->control, D64_XC_AE);
-       w = R_REG(&dma64regs->control);
-       AND_REG(&dma64regs->control, ~D64_XC_AE);
+       bcma_set32(di->d11core, ctrl_offset, D64_XC_AE);
+       w = bcma_read32(di->d11core, ctrl_offset);
+       bcma_mask32(di->d11core, ctrl_offset, ~D64_XC_AE);
        return (w & D64_XC_AE) == D64_XC_AE;
 }
 
        /* DMA64 supports full 32- or 64-bit operation. AE is always valid */
 
        /* not all tx or rx channel are available */
-       if (di->d64txregs != NULL) {
-               if (!_dma64_addrext(di->d64txregs))
+       if (di->d64txregbase != 0) {
+               if (!_dma64_addrext(di, DMA64TXREGOFFS(di, control)))
                        DMA_ERROR("%s: DMA64 tx doesn't have AE set\n",
                                  di->name);
                return true;
-       } else if (di->d64rxregs != NULL) {
-               if (!_dma64_addrext(di->d64rxregs))
+       } else if (di->d64rxregbase != 0) {
+               if (!_dma64_addrext(di, DMA64RXREGOFFS(di, control)))
                        DMA_ERROR("%s: DMA64 rx doesn't have AE set\n",
                                  di->name);
                return true;
        u32 addrl;
 
        /* Check to see if the descriptors need to be aligned on 4K/8K or not */
-       if (di->d64txregs != NULL) {
-               W_REG(&di->d64txregs->addrlow, 0xff0);
-               addrl = R_REG(&di->d64txregs->addrlow);
+       if (di->d64txregbase != 0) {
+               bcma_write32(di->d11core, DMA64TXREGOFFS(di, addrlow), 0xff0);
+               addrl = bcma_read32(di->d11core, DMA64TXREGOFFS(di, addrlow));
                if (addrl != 0)
                        return false;
-       } else if (di->d64rxregs != NULL) {
-               W_REG(&di->d64rxregs->addrlow, 0xff0);
-               addrl = R_REG(&di->d64rxregs->addrlow);
+       } else if (di->d64rxregbase != 0) {
+               bcma_write32(di->d11core, DMA64RXREGOFFS(di, addrlow), 0xff0);
+               addrl = bcma_read32(di->d11core, DMA64RXREGOFFS(di, addrlow));
                if (addrl != 0)
                        return false;
        }
 
 struct dma_pub *dma_attach(char *name, struct si_pub *sih,
                           struct bcma_device *d11core,
-                          void __iomem *dmaregstx, void __iomem *dmaregsrx,
-                          uint ntxd, uint nrxd,
+                          uint txregbase, uint rxregbase, uint ntxd, uint nrxd,
                           uint rxbufsize, int rxextheadroom,
                           uint nrxpost, uint rxoffset, uint *msg_level)
 {
 
        di->dma64 = ((ai_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
 
-       /* init dma reg pointer */
+       /* init dma reg info */
        di->d11core = d11core;
-       di->d64txregs = (struct dma64regs __iomem *) dmaregstx;
-       di->d64rxregs = (struct dma64regs __iomem *) dmaregsrx;
+       di->d64txregbase = txregbase;
+       di->d64rxregbase = rxregbase;
 
        /*
         * Default flags (which can be changed by the driver calling
         */
        _dma_ctrlflags(di, DMA_CTRL_ROC | DMA_CTRL_PEN, 0);
 
-       DMA_TRACE("%s: %s flags 0x%x ntxd %d nrxd %d rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d dmaregstx %p dmaregsrx %p\n",
-                 name, "DMA64",
+       DMA_TRACE("%s: %s flags 0x%x ntxd %d nrxd %d "
+                 "rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d "
+                 "txregbase %u rxregbase %u\n", name, "DMA64",
                  di->dma.dmactrlflags, ntxd, nrxd, rxbufsize,
-                 rxextheadroom, nrxpost, rxoffset, dmaregstx, dmaregsrx);
+                 rxextheadroom, nrxpost, rxoffset, txregbase, rxregbase);
 
        /* make a private copy of our callers name */
        strncpy(di->name, name, MAXNAMEL);
        if ((di->ddoffsetlow == 0)
            || !(pa & PCI32ADDR_HIGH)) {
                if (direction == DMA_TX) {
-                       W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
-                       W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
+                       bcma_write32(di->d11core, DMA64TXREGOFFS(di, addrlow),
+                                    pa + di->ddoffsetlow);
+                       bcma_write32(di->d11core, DMA64TXREGOFFS(di, addrhigh),
+                                    di->ddoffsethigh);
                } else {
-                       W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
-                       W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
+                       bcma_write32(di->d11core, DMA64RXREGOFFS(di, addrlow),
+                                    pa + di->ddoffsetlow);
+                       bcma_write32(di->d11core, DMA64RXREGOFFS(di, addrhigh),
+                                    di->ddoffsethigh);
                }
        } else {
                /* DMA64 32bits address extension */
                pa &= ~PCI32ADDR_HIGH;
 
                if (direction == DMA_TX) {
-                       W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
-                       W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
-                       SET_REG(&di->d64txregs->control,
-                               D64_XC_AE, (ae << D64_XC_AE_SHIFT));
+                       bcma_write32(di->d11core, DMA64TXREGOFFS(di, addrlow),
+                                    pa + di->ddoffsetlow);
+                       bcma_write32(di->d11core, DMA64TXREGOFFS(di, addrhigh),
+                                    di->ddoffsethigh);
+                       bcma_maskset32(di->d11core, DMA64TXREGOFFS(di, control),
+                                      D64_XC_AE, (ae << D64_XC_AE_SHIFT));
                } else {
-                       W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
-                       W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
-                       SET_REG(&di->d64rxregs->control,
-                               D64_RC_AE, (ae << D64_RC_AE_SHIFT));
+                       bcma_write32(di->d11core, DMA64RXREGOFFS(di, addrlow),
+                                    pa + di->ddoffsetlow);
+                       bcma_write32(di->d11core, DMA64RXREGOFFS(di, addrhigh),
+                                    di->ddoffsethigh);
+                       bcma_maskset32(di->d11core, DMA64RXREGOFFS(di, control),
+                                      D64_RC_AE, (ae << D64_RC_AE_SHIFT));
                }
        }
 }
 
        DMA_TRACE("%s:\n", di->name);
 
-       control =
-           (R_REG(&di->d64rxregs->control) & D64_RC_AE) |
-           D64_RC_RE;
+       control = D64_RC_RE | (bcma_read32(di->d11core,
+                                          DMA64RXREGOFFS(di, control)) &
+                              D64_RC_AE);
 
        if ((dmactrlflags & DMA_CTRL_PEN) == 0)
                control |= D64_RC_PD;
        if (dmactrlflags & DMA_CTRL_ROC)
                control |= D64_RC_OC;
 
-       W_REG(&di->d64rxregs->control,
+       bcma_write32(di->d11core, DMA64RXREGOFFS(di, control),
                ((di->rxoffset << D64_RC_RO_SHIFT) | control));
 }
 
                return NULL;
 
        curr =
-           B2I(((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) -
+           B2I(((bcma_read32(di->d11core,
+                             DMA64RXREGOFFS(di, status0)) & D64_RS0_CD_MASK) -
                 di->rcvptrbase) & D64_RS0_CD_MASK, struct dma64desc);
 
        /* ignore curr if forceall */
                if (resid > 0) {
                        uint cur;
                        cur =
-                           B2I(((R_REG(&di->d64rxregs->status0) &
-                                 D64_RS0_CD_MASK) -
-                                di->rcvptrbase) & D64_RS0_CD_MASK,
-                               struct dma64desc);
+                           B2I(((bcma_read32(di->d11core,
+                                             DMA64RXREGOFFS(di, status0)) &
+                                 D64_RS0_CD_MASK) - di->rcvptrbase) &
+                               D64_RS0_CD_MASK, struct dma64desc);
                        DMA_ERROR("rxin %d rxout %d, hw_curr %d\n",
-                                 di->rxin, di->rxout, cur);
+                                  di->rxin, di->rxout, cur);
                }
 #endif                         /* BCMDBG */
 
        if (di->nrxd == 0)
                return true;
 
-       return ((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
-               (R_REG(&di->d64rxregs->ptr) & D64_RS0_CD_MASK));
+       return ((bcma_read32(di->d11core,
+                            DMA64RXREGOFFS(di, status0)) & D64_RS0_CD_MASK) ==
+               (bcma_read32(di->d11core, DMA64RXREGOFFS(di, ptr)) &
+                D64_RS0_CD_MASK));
 }
 
 /*
        di->rxout = rxout;
 
        /* update the chip lastdscr pointer */
-       W_REG(&di->d64rxregs->ptr,
+       bcma_write32(di->d11core, DMA64RXREGOFFS(di, ptr),
              di->rcvptrbase + I2B(rxout, struct dma64desc));
 
        return ring_empty;
 
        if ((di->dma.dmactrlflags & DMA_CTRL_PEN) == 0)
                control |= D64_XC_PD;
-       OR_REG(&di->d64txregs->control, control);
+       bcma_set32(di->d11core, DMA64TXREGOFFS(di, control), control);
 
        /* DMA engine with alignment requirement requires table to be inited
         * before enabling the engine
        if (di->ntxd == 0)
                return;
 
-       OR_REG(&di->d64txregs->control, D64_XC_SE);
+       bcma_set32(di->d11core, DMA64TXREGOFFS(di, control), D64_XC_SE);
 }
 
 void dma_txresume(struct dma_pub *pub)
        if (di->ntxd == 0)
                return;
 
-       AND_REG(&di->d64txregs->control, ~D64_XC_SE);
+       bcma_mask32(di->d11core, DMA64TXREGOFFS(di, control), ~D64_XC_SE);
 }
 
 bool dma_txsuspended(struct dma_pub *pub)
        struct dma_info *di = (struct dma_info *)pub;
 
        return (di->ntxd == 0) ||
-           ((R_REG(&di->d64txregs->control) & D64_XC_SE) ==
-            D64_XC_SE);
+              ((bcma_read32(di->d11core,
+                            DMA64TXREGOFFS(di, control)) & D64_XC_SE) ==
+               D64_XC_SE);
 }
 
 void dma_txreclaim(struct dma_pub *pub, enum txd_range range)
                return true;
 
        /* suspend tx DMA first */
-       W_REG(&di->d64txregs->control, D64_XC_SE);
+       bcma_write32(di->d11core, DMA64TXREGOFFS(di, control), D64_XC_SE);
        SPINWAIT(((status =
-                  (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
-                 != D64_XS0_XS_DISABLED) && (status != D64_XS0_XS_IDLE)
-                && (status != D64_XS0_XS_STOPPED), 10000);
+                  (bcma_read32(di->d11core, DMA64TXREGOFFS(di, status0)) &
+                   D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED) &&
+                 (status != D64_XS0_XS_IDLE) && (status != D64_XS0_XS_STOPPED),
+                10000);
 
-       W_REG(&di->d64txregs->control, 0);
+       bcma_write32(di->d11core, DMA64TXREGOFFS(di, control), 0);
        SPINWAIT(((status =
-                  (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
-                 != D64_XS0_XS_DISABLED), 10000);
+                  (bcma_read32(di->d11core, DMA64TXREGOFFS(di, status0)) &
+                   D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED), 10000);
 
        /* wait for the last transaction to complete */
        udelay(300);
        if (di->nrxd == 0)
                return true;
 
-       W_REG(&di->d64rxregs->control, 0);
+       bcma_write32(di->d11core, DMA64RXREGOFFS(di, control), 0);
        SPINWAIT(((status =
-                  (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK))
-                 != D64_RS0_RS_DISABLED), 10000);
+                  (bcma_read32(di->d11core, DMA64RXREGOFFS(di, status0)) &
+                   D64_RS0_RS_MASK)) != D64_RS0_RS_DISABLED), 10000);
 
        return status == D64_RS0_RS_DISABLED;
 }
 
        /* kick the chip */
        if (commit)
-               W_REG(&di->d64txregs->ptr,
+               bcma_write32(di->d11core, DMA64TXREGOFFS(di, ptr),
                      di->xmtptrbase + I2B(txout, struct dma64desc));
 
        /* tx flow control */
        if (range == DMA_RANGE_ALL)
                end = di->txout;
        else {
-               struct dma64regs __iomem *dregs = di->d64txregs;
-
-               end = (u16) (B2I(((R_REG(&dregs->status0) &
-                                D64_XS0_CD_MASK) -
-                                di->xmtptrbase) & D64_XS0_CD_MASK,
-                                struct dma64desc));
+               end = (u16) (B2I(((bcma_read32(di->d11core,
+                                              DMA64TXREGOFFS(di, status0)) &
+                                  D64_XS0_CD_MASK) - di->xmtptrbase) &
+                                D64_XS0_CD_MASK, struct dma64desc));
 
                if (range == DMA_RANGE_TRANSFERED) {
                        active_desc =
-                           (u16) (R_REG(&dregs->status1) &
+                               (u16)(bcma_read32(di->d11core,
+                                                 DMA64TXREGOFFS(di, status1)) &
                                      D64_XS1_AD_MASK);
                        active_desc =
                            (active_desc - di->xmtptrbase) & D64_XS0_CD_MASK;