* device
*
* The "global interrupt mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_ENABLE and ARMADA_370_XP_INT_CLEAR_ENABLE
+ * MPIC_INT_SET_ENABLE and MPIC_INT_CLEAR_ENABLE
* registers, which are relative to "main_int_base".
*
- * The "per-CPU mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_MASK and ARMADA_370_XP_INT_CLEAR_MASK
- * registers, which are relative to "per_cpu_int_base". This base
- * address points to a special address, which automatically accesses
- * the registers of the current CPU.
+ * The "per-CPU mask/unmask" is modified using the MPIC_INT_SET_MASK
+ * and MPIC_INT_CLEAR_MASK registers, which are relative to
+ * "per_cpu_int_base". This base address points to a special address,
+ * which automatically accesses the registers of the current CPU.
*
* The per-CPU mask/unmask can also be adjusted using the global
- * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
- * to configure interrupt affinity.
+ * per-interrupt MPIC_INT_SOURCE_CTL register, which we use to
+ * configure interrupt affinity.
*
* Due to this model, all interrupts need to be mask/unmasked at two
* different levels: at the global level and at the per-CPU level.
* the current CPU, running the ->map() code. This allows to have
* the interrupt unmasked at this level in non-SMP
* configurations. In SMP configurations, the ->set_affinity()
- * callback is called, which using the
- * ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
- * for the interrupt.
+ * callback is called, which using the MPIC_INT_SOURCE_CTL()
+ * readjusts the per-CPU mask/unmask for the interrupt.
*
* The ->mask() and ->unmask() operations only mask/unmask the
* interrupt at the "global" level.
*/
/* Registers relative to main_int_base */
-#define ARMADA_370_XP_INT_CONTROL 0x00
-#define ARMADA_370_XP_SW_TRIG_INT 0x04
-#define ARMADA_370_XP_INT_SET_ENABLE 0x30
-#define ARMADA_370_XP_INT_CLEAR_ENABLE 0x34
-#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + (irq) * 4)
-#define ARMADA_370_XP_INT_SOURCE_CPU_MASK GENMASK(3, 0)
-#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << (cpuid))
+#define MPIC_INT_CONTROL 0x00
+#define MPIC_SW_TRIG_INT 0x04
+#define MPIC_INT_SET_ENABLE 0x30
+#define MPIC_INT_CLEAR_ENABLE 0x34
+#define MPIC_INT_SOURCE_CTL(irq) (0x100 + (irq) * 4)
+#define MPIC_INT_SOURCE_CPU_MASK GENMASK(3, 0)
+#define MPIC_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << (cpuid))
/* Registers relative to per_cpu_int_base */
-#define ARMADA_370_XP_IN_DRBEL_CAUSE 0x08
-#define ARMADA_370_XP_IN_DRBEL_MASK 0x0c
-#define ARMADA_375_PPI_CAUSE 0x10
-#define ARMADA_370_XP_CPU_INTACK 0x44
-#define ARMADA_370_XP_INT_SET_MASK 0x48
-#define ARMADA_370_XP_INT_CLEAR_MASK 0x4C
-#define ARMADA_370_XP_INT_FABRIC_MASK 0x54
-#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) BIT(cpu)
+#define MPIC_IN_DRBEL_CAUSE 0x08
+#define MPIC_IN_DRBEL_MASK 0x0c
+#define MPIC_PPI_CAUSE 0x10
+#define MPIC_CPU_INTACK 0x44
+#define MPIC_INT_SET_MASK 0x48
+#define MPIC_INT_CLEAR_MASK 0x4C
+#define MPIC_INT_FABRIC_MASK 0x54
+#define MPIC_INT_CAUSE_PERF(cpu) BIT(cpu)
-#define ARMADA_370_XP_MAX_PER_CPU_IRQS 28
+#define MPIC_MAX_PER_CPU_IRQS 28
/* IPI and MSI interrupt definitions for IPI platforms */
#define IPI_DOORBELL_START 0
static inline bool is_percpu_irq(irq_hw_number_t irq)
{
- if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
+ if (irq <= MPIC_MAX_PER_CPU_IRQS)
return true;
return false;
irq_hw_number_t hwirq = irqd_to_hwirq(d);
if (!is_percpu_irq(hwirq))
- writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
+ writel(hwirq, main_int_base + MPIC_INT_CLEAR_ENABLE);
else
- writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
+ writel(hwirq, per_cpu_int_base + MPIC_INT_SET_MASK);
}
static void armada_370_xp_irq_unmask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
if (!is_percpu_irq(hwirq))
- writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
+ writel(hwirq, main_int_base + MPIC_INT_SET_ENABLE);
else
- writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+ writel(hwirq, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
}
#ifdef CONFIG_PCI_MSI
u32 reg;
/* Enable MSI doorbell mask and combined cpu local interrupt */
- reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+ reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
reg |= msi_doorbell_mask();
- writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+ writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
/* Unmask local doorbell interrupt */
- writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+ writel(1, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
}
static int armada_370_xp_msi_init(struct device_node *node,
phys_addr_t main_int_phys_base)
{
- msi_doorbell_addr = main_int_phys_base + ARMADA_370_XP_SW_TRIG_INT;
+ msi_doorbell_addr = main_int_phys_base + MPIC_SW_TRIG_INT;
armada_370_xp_msi_inner_domain =
irq_domain_add_linear(NULL, msi_doorbell_size(),
/* Unmask low 16 MSI irqs on non-IPI platforms */
if (!is_ipi_available())
- writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+ writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
return 0;
}
cpuid = cpu_logical_map(smp_processor_id());
/* Enable Performance Counter Overflow interrupts */
- writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
- per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK);
+ writel(MPIC_INT_CAUSE_PERF(cpuid),
+ per_cpu_int_base + MPIC_INT_FABRIC_MASK);
}
#ifdef CONFIG_SMP
static void armada_370_xp_ipi_mask(struct irq_data *d)
{
u32 reg;
- reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+ reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
reg &= ~BIT(d->hwirq);
- writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+ writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
}
static void armada_370_xp_ipi_unmask(struct irq_data *d)
{
u32 reg;
- reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+ reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
reg |= BIT(d->hwirq);
- writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+ writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
}
static void armada_370_xp_ipi_send_mask(struct irq_data *d,
dsb();
/* submit softirq */
- writel((map << 8) | d->hwirq, main_int_base +
- ARMADA_370_XP_SW_TRIG_INT);
+ writel((map << 8) | d->hwirq, main_int_base + MPIC_SW_TRIG_INT);
}
static void armada_370_xp_ipi_ack(struct irq_data *d)
{
- writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+ writel(~BIT(d->hwirq), per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
}
static struct irq_chip ipi_irqchip = {
/* Select a single core from the affinity mask which is online */
cpu = cpumask_any_and(mask_val, cpu_online_mask);
- atomic_io_modify(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq),
- ARMADA_370_XP_INT_SOURCE_CPU_MASK,
- BIT(cpu_logical_map(cpu)));
+ atomic_io_modify(main_int_base + MPIC_INT_SOURCE_CTL(hwirq),
+ MPIC_INT_SOURCE_CPU_MASK, BIT(cpu_logical_map(cpu)));
irq_data_update_effective_affinity(d, cpumask_of(cpu));
u32 control;
int nr_irqs, i;
- control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
+ control = readl(main_int_base + MPIC_INT_CONTROL);
nr_irqs = (control >> 2) & 0x3ff;
for (i = 0; i < nr_irqs; i++)
- writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
+ writel(i, per_cpu_int_base + MPIC_INT_SET_MASK);
if (!is_ipi_available())
return;
/* Disable all IPIs */
- writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+ writel(0, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
/* Clear pending IPIs */
- writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+ writel(0, per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
/* Unmask IPI interrupt */
- writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+ writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
}
static void armada_xp_mpic_reenable_percpu(void)
unsigned int irq;
/* Re-enable per-CPU interrupts that were enabled before suspend */
- for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
+ for (irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) {
struct irq_data *data;
int virq;
armada_370_xp_irq_mask(irq_get_irq_data(virq));
if (!is_percpu_irq(hw))
- writel(hw, per_cpu_int_base +
- ARMADA_370_XP_INT_CLEAR_MASK);
+ writel(hw, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
else
- writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
+ writel(hw, main_int_base + MPIC_INT_SET_ENABLE);
irq_set_status_flags(virq, IRQ_LEVEL);
if (is_percpu_irq(hw)) {
{
u32 msimask, msinr;
- msimask = readl_relaxed(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+ msimask = readl_relaxed(per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
msimask &= msi_doorbell_mask();
- writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+ writel(~msimask, per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
for (msinr = msi_doorbell_start();
msinr < msi_doorbell_end(); msinr++) {
chained_irq_enter(chip, desc);
- irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
+ irqmap = readl_relaxed(per_cpu_int_base + MPIC_PPI_CAUSE);
cpuid = cpu_logical_map(smp_processor_id());
for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
- irqsrc = readl_relaxed(main_int_base +
- ARMADA_370_XP_INT_SOURCE_CTL(irqn));
+ irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(irqn));
/* Check if the interrupt is not masked on current CPU.
* Test IRQ (0-1) and FIQ (8-9) mask bits.
*/
- if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
+ if (!(irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)))
continue;
if (irqn == 0 || irqn == 1) {
u32 irqstat, irqnr;
do {
- irqstat = readl_relaxed(per_cpu_int_base +
- ARMADA_370_XP_CPU_INTACK);
+ irqstat = readl_relaxed(per_cpu_int_base + MPIC_CPU_INTACK);
irqnr = irqstat & 0x3FF;
if (irqnr > 1022)
int ipi;
ipimask = readl_relaxed(per_cpu_int_base +
- ARMADA_370_XP_IN_DRBEL_CAUSE)
+ MPIC_IN_DRBEL_CAUSE)
& IPI_DOORBELL_MASK;
for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
static int armada_370_xp_mpic_suspend(void)
{
- doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+ doorbell_mask_reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
return 0;
}
irq_hw_number_t irq;
/* Re-enable interrupts */
- nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
+ nirqs = (readl(main_int_base + MPIC_INT_CONTROL) >> 2) & 0x3ff;
for (irq = 0; irq < nirqs; irq++) {
struct irq_data *data;
int virq;
if (!is_percpu_irq(irq)) {
/* Non per-CPU interrupts */
- writel(irq, per_cpu_int_base +
- ARMADA_370_XP_INT_CLEAR_MASK);
+ writel(irq, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
if (!irqd_irq_disabled(data))
armada_370_xp_irq_unmask(data);
} else {
/* Per-CPU interrupts */
- writel(irq, main_int_base +
- ARMADA_370_XP_INT_SET_ENABLE);
+ writel(irq, main_int_base + MPIC_INT_SET_ENABLE);
/*
* Re-enable on the current CPU,
}
/* Reconfigure doorbells for IPIs and MSIs */
- writel(doorbell_mask_reg,
- per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+ writel(doorbell_mask_reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
if (is_ipi_available()) {
src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;
}
if (src0)
- writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+ writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
if (src1)
- writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+ writel(1, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
if (is_ipi_available())
ipi_resume();
resource_size(&per_cpu_int_res));
BUG_ON(!per_cpu_int_base);
- control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
+ control = readl(main_int_base + MPIC_INT_CONTROL);
nr_irqs = (control >> 2) & 0x3ff;
for (i = 0; i < nr_irqs; i++)
- writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
+ writel(i, main_int_base + MPIC_INT_CLEAR_ENABLE);
armada_370_xp_mpic_domain =
irq_domain_add_linear(node, nr_irqs,
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