if (is_eth) {
                        wc->sl  = be16_to_cpu(cqe->sl_vid) >> 13;
                        if (be32_to_cpu(cqe->vlan_my_qpn) &
-                                       MLX4_CQE_VLAN_PRESENT_MASK) {
+                                       MLX4_CQE_CVLAN_PRESENT_MASK) {
                                wc->vlan_id = be16_to_cpu(cqe->sl_vid) &
                                        MLX4_CQE_VID_MASK;
                        } else {
 
 
        hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 
-       if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK) &&
+       if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
            !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
                hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
                hdr += sizeof(struct vlan_hdr);
                                gro_skb->csum_level = 1;
 
                        if ((cqe->vlan_my_qpn &
-                           cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) &&
+                           cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
                            (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
                                u16 vid = be16_to_cpu(cqe->sl_vid);
 
                                        PKT_HASH_TYPE_L3);
 
                if ((be32_to_cpu(cqe->vlan_my_qpn) &
-                   MLX4_CQE_VLAN_PRESENT_MASK) &&
+                   MLX4_CQE_CVLAN_PRESENT_MASK) &&
                    (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
                        __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
 
 
                ring->bf.offset ^= ring->bf.buf_size;
        } else {
                tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
-               tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
+               tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN *
                        !!skb_vlan_tag_present(skb);
                tx_desc->ctrl.fence_size = real_size;
 
 
 
 enum {
        MLX4_CQE_L2_TUNNEL_IPOK         = 1 << 31,
-       MLX4_CQE_VLAN_PRESENT_MASK      = 1 << 29,
+       MLX4_CQE_CVLAN_PRESENT_MASK     = 1 << 29,
        MLX4_CQE_L2_TUNNEL              = 1 << 27,
        MLX4_CQE_L2_TUNNEL_CSUM         = 1 << 26,
        MLX4_CQE_L2_TUNNEL_IPV4         = 1 << 25,
 
        MLX4_WQE_CTRL_SOLICITED         = 1 << 1,
        MLX4_WQE_CTRL_IP_CSUM           = 1 << 4,
        MLX4_WQE_CTRL_TCP_UDP_CSUM      = 1 << 5,
-       MLX4_WQE_CTRL_INS_VLAN          = 1 << 6,
+       MLX4_WQE_CTRL_INS_CVLAN         = 1 << 6,
        MLX4_WQE_CTRL_STRONG_ORDER      = 1 << 7,
        MLX4_WQE_CTRL_FORCE_LOOPBACK    = 1 << 0,
 };