/*
  * The IRQs are mapped as:
  *
- *     ======================  =============   ============    =====
- *     IRQ                     MASK REGISTER   IRQ REGISTER    BIT
- *     ======================  =============   ============    =====
+ *     ======================  =============   ============    =====
+ *     IRQ                     MASK REGISTER   IRQ REGISTER    BIT
+ *     ======================  =============   ============    =====
  *     OTMP                    0x0202          0x212           bit 0
  *     VBUS_CONNECT            0x0202          0x212           bit 1
  *     VBUS_DISCONNECT         0x0202          0x212           bit 2
  *     SIM0_HPD_F              0x0203          0x213           bit 3
  *     SIM1_HPD_R              0x0203          0x213           bit 4
  *     SIM1_HPD_F              0x0203          0x213           bit 5
- *     ======================  =============   ============    =====
+ *     ======================  =============   ============    =====
  */
 #define SOC_PMIC_IRQ_MASK_0_ADDR       0x0202
 #define SOC_PMIC_IRQ0_ADDR             0x0212